37.2.2 Extended Instruction Set


ADDFSR	Add Literal to FSR
Syntax:	ADDFSR f, k
Operands:	0 ≤ k ≤ 63 f ∈ [ 0, 1, 2 ]
Operation:	FSR(f) + k → FSR(f)
Status Affected:	None
Encoding:	1110	1000	ffkk	kkkk
Description:	The 6-bit literal ‘k’ is added to the contents of the FSR specified by ‘f’.
Words:	1
Cycles:	1


Q Cycle Activity:
	Q1	Q2	Q3	Q4
	Decode	Read literal ‘k’	Process Data	Write to  FSR


Example:	ADDFSR 2, 23h
Before Instruction FSR2 = 03FFh After Instruction FSR2 = 0422h


ADDULNK	Add Literal to FSR2 and Return
Syntax:	ADDULNK k
Operands:	0 ≤ k ≤ 63
Operation:	FSR2 + k → FSR2,
	(TOS) → PC
Status Affected:	None
Encoding:	1110	1000	11kk	kkkk
Description:	The 6-bit literal ‘k’ is added to the contents of FSR2. A RETURN is then executed by loading the PC with the TOS. The instruction takes two cycles to execute; a `NOP` is performed during the second cycle. This may be thought of as a special case of the ADDFSR instruction, where f = 3 (binary ‘11’); it operates only on FSR2.
Words:	1
Cycles:	2


Q Cycle Activity:
	Q1	Q2	Q3	Q4
	Decode	Read literal ‘k’	Process Data	Write to  FSR
	No  Operation	No  Operation	No  Operation	No  Operation


Example:	ADDULNK 23h
Before Instruction FSR2 = 03FFh PC = 0100h After Instruction FSR2 = 0422h PC = (TOS)

Important: All PIC18 instructions may take an optional label argument preceding the instruction mnemonic for use in symbolic addressing. If a label is used, the instruction syntax then becomes: {label} instruction argument(s).


CALLW	Subroutine Call Using WREG
Syntax:	CALLW
Operands:	None
Operation:	(PC + 2) → TOS, (W) → PCL, (PCLATH) → PCH, (PCLATU) → PCU
Status Affected:	None
Encoding:	0000	0000	0001	0100
Description	First, the return address (PC + 2) is pushed onto the return stack. Next, the contents of W are written to PCL; the existing value is discarded. Then, the contents of PCLATH and PCLATU are latched onto PCH and PCU,  respectively. The second cycle is  executed as a `NOP` instruction while the new next instruction is fetched. Unlike CALL, there is no option to update W, Status or BSR.
Words:	1
Cycles:	2


Q Cycle Activity:
	Q1	Q2	Q3	Q4
	Decode	Read  WREG	PUSH PC to stack	No  operation
	No  operation	No  operation	No  operation	No  operation


Example:	`HERE`	`CALLW`
Before Instruction PC = address (HERE) PCLATH = 10h PCLATU = 00h W = 06h After Instruction PC = 001006h TOS = address (HERE + 2) PCLATH = 10h PCLATU = 00h W = 06h


MOVSF	Move Indexed to f
Syntax:	MOVSF [z_s], f_d
Operands:	0 ≤ z_s ≤ 127 0 ≤ f_d ≤ 4095
Operation:	((FSR2) + z_s) → f_d
Status Affected:	None
Encoding: 1st word (source) 2nd word (destin.)	1110 1111	1011 ffff	0zzz ffff	zzzz_s ffff_d
Description:	The contents of the source register are moved to destination register ‘f_d’. The actual address of the source register is determined by adding the 7-bit literal offset ‘z_s’ in the first word to the value of FSR2. The address of the destination register is specified by the 12-bit literal ‘f_d’ in the second word. Both addresses can be anywhere in the 4096-byte data space (000h to FFFh). The `MOVSF` instruction cannot use the PCL, TOSU, TOSH or TOSL as the destination register. If the resultant source address points to an Indirect Addressing register, the value returned will be 00h.
Words:	2
Cycles:	2


Q Cycle Activity:
	Q1	Q2	Q3	Q4
	Decode	Determine source addr	Determine source addr	Read  source reg
	Decode	No  operation No dummy read	No  operation	Write  register ‘f’ (dest)


Example:	`MOVSF [05h], REG2`
Before Instruction FSR2 = 80h Contents  of 85h = 33h REG2 = 11h After Instruction FSR2 = 80h Contents  of 85h = 33h REG2 = 33h


MOVSS	Move Indexed to Indexed
Syntax:	MOVSS [z_s], [z_d]
Operands:	0 ≤ z_s ≤ 127 0 ≤ z_d ≤ 127
Operation:	((FSR2) + z_s) → ((FSR2) + z_d)
Status Affected:	None
Encoding: 1st word (source) 2nd word (dest.)	1110 1111	1011 xxxx	1zzz xzzz	zzzz_s zzzz_d
Description	The contents of the source register are moved to the destination register. The addresses of the source and destination registers are determined by adding the 7-bit literal offsets ‘z_s’ or ‘z_d’,  respectively, to the value of FSR2. Both registers can be located anywhere in the 4096-byte data memory space (000h to FFFh). The MOVSS instruction cannot use the PCL, TOSU, TOSH or TOSL as the destination register. If the resultant source address points to an Indirect Addressing register, the value returned will be 00h. If the  resultant destination address points to an Indirect Addressing register, the instruction will execute as a `NOP`.
Words:	2
Cycles:	2


Q Cycle Activity:
	Q1	Q2	Q3	Q4
	Decode	Determine source addr	Determine source addr	Read  source reg
	Decode	Determine dest addr	Determine dest addr	Write  to dest reg


Example:	`MOVSS [05h], [06h]`
Before Instruction FSR2 = 80h Contents of 85h = 33h Contents of 86h = 11h After Instruction FSR2 = 80h Contents of 85h = 33h Contents of 86h = 33h


PUSHL	Store Literal at FSR2, Decrement FSR2
Syntax:	PUSHL k
Operands:	0 ≤ k ≤ 255
Operation:	k → (FSR2), FSR2 – 1 → FSR2
Status Affected:	None
Encoding:	1111	1010	kkkk	kkkk
Description:	The 8-bit literal ‘k’ is written to the data memory address specified by FSR2. FSR2 is decremented by 1 after the operation. This instruction allows users to push values onto a software stack.
Words:	1
Cycles:	1


Q Cycle Activity:
	Q1	Q2	Q3	Q4
	Decode	Read ‘k’	Process data	Write to destination


Example:	`PUSHL 08h`
Before Instruction FSR2H:FSR2L = 01ECh Memory (01ECh) = 00h After Instruction FSR2H:FSR2L = 01EBh Memory (01ECh) = 08h


SUBFSR	Subtract Literal from FSR
Syntax:	SUBFSR f, k
Operands:	0 ≤ k ≤ 63
Operands:	f ∈ [ 0, 1, 2 ]
Operation:	FSR(f) – k → FSRf
Status Affected:	None
Encoding:	1110	1001	ffkk	kkkk
Description:	The 6-bit literal ‘k’ is subtracted from the contents of the FSR specified by ‘f’.
Words:	1
Cycles:	1


Q Cycle Activity:
	Q1	Q2	Q3	Q4
	Decode	Read register ‘f’	Process Data	Write to  destination


Example:	SUBFSR 2, 23h
Before Instruction FSR2 = 03FFh After Instruction FSR2 = 03DCh


SUBULNK	Subtract Literal from FSR2 and Return
Syntax:	SUBULNK k
Operands:	0 ≤ k ≤ 63
Operation:	FSR2 – k → FSR2
Operation:	(TOS) → PC
Status Affected:	None
Encoding:	1110	1001	11kk	kkkk
Description:	The 6-bit literal ‘k’ is subtracted from the contents of the FSR2. A RETURN is then executed by loading the PC with the TOS. The instruction takes two cycles to  execute; a `NOP` is performed during the second cycle. This may be thought of as a special case of the SUBFSR instruction, where f = 3 (binary ‘11’); it operates only on FSR2.
Words:	1
Cycles:	2


Q Cycle Activity:
	Q1	Q2	Q3	Q4
	Decode	Read register ‘f’	Process Data	Write to  destination
	No Operation	No Operation	No Operation	No Operation


Example:	SUBULNK 23h
Before Instruction FSR2 = 03FFh PC = 0100h After Instruction FSR2 = 03DCh PC = (TOS)

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