7.2 Sleep Mode

Sleep mode is entered by executing the SLEEP instruction, while the Idle Enable (IDLEN) bit of the CPUDOZE register is cleared (IDLEN = 0). If the SLEEP instruction is executed while the IDLEN bit is set (IDLEN = 1), the CPU will enter the Idle mode.

Upon entering Sleep mode, the following conditions exist:

  1. Resets other than WDT are not affected by Sleep mode; WDT will be cleared but keeps running if enabled for operation during Sleep.
  2. The PD bit of the STATUS register is cleared.
  3. The TO bit of the STATUS register is set.
  4. The CPU and the System clocks are disabled.
  5. 31 kHz LFINTOSC, HFINTOSC and SOSC will remain enabled if any peripheral has requested them as a clock source or if the HFOEN, LFOEN, or SOSCEN bits of the OSCEN register are set.
  6. ADC is unaffected if the FRC oscillator is selected. When the ADC clock is something other than FRC, a SLEEP instruction causes the present conversion to be aborted and the ADC module is turned off, although the ADON bit remains active.
  7. I/O ports maintain the status they had before SLEEP was executed (driving high, low, or high-impedance) only if no peripheral connected to the I/O port is active.

Refer to individual chapters for more details on peripheral operation during Sleep.

To minimize current consumption, consider the following conditions:

  • I/O pins must not be floating
  • External circuitry sinking current from I/O pins
  • Internal circuitry sourcing current from I/O pins
  • Current draw from pins with internal weak pull-ups
  • Modules using any oscillator

I/O pins that are high-impedance inputs need to be pulled to VDD or VSS externally to avoid switching currents caused by floating inputs.

Examples of internal circuitry that might be sourcing current include modules such as the DAC and FVR modules.