3 System Controller Suspend Mode

To protect the device from unintended behavior due to single event upset (SEU), the system controller can be held in Suspend mode after device initialization. The system controller is active if the device is power-cycled or if a hard reset is applied. But it returns to Suspend Mode, once the initialization cycle is completed. A Sonos bit that is programmed during device programming controls the System Controller Suspend Mode. This Sonos bit is not accessible from the customer design or by any external pin. The flash bit is only accessible through the programming file loaded into the device.

As the control bit is stored in a flash cell, it is immune to radiation effects due to the following:

• Neutrons or alpha particles in terrestrial and airborne applications
• Heavy ions in space applications

While the FPGA is in System Controller Suspend Mode, programming via JTAG or SPI-Slave mode can be accomplished, by asserting the JTAG_TRSTB pin HIGH, to temporarily remove the FPGA from System Controller Suspend Mode. If the JTAG_TRSTB pin is LOW, all the other JTAG input signals are blocked from activating the system controller.

For programming, run Scan Chain using FlashPro software (from the Menu bar, click Programmers > Scan Chain), which keeps the JTAG_TRSTB pin HIGH. Keeping the JTAG_TRSTB pin HIGH causes system controller to exit from Suspend Mode and then program the device.

When in space, the JTAG_TRSTB pin must be held LOW using one of the following methods:

• Hardwired to ground
• Connected to ground through a jumper
• Tied to ground through a pull-down, if an active device is included in the circuit to allow on-orbit reprogramming

To restore normal operation, the device must be reprogrammed using the JTAG port with the System Controller Suspend Mode bit turned off, that is, disable the System Controller Suspend Mode in Libero SoC software, regenerate the bitstream, and reprogram the device.

When RT PolarFire FPGAs are used in System Controller Suspend Mode, device programming is disabled to protect the device from unintended programming because of SEUs. After device initialization, the system controller is held in Reset state and cannot provide system services such as security, IAP, or auto update programming. After the device exits the System Controller Suspend Mode, it can be programmed as usual. For a full listing of device feature availability in System Controller Suspend Mode, and suspend mode operation, see PolarFire FPGA and PolarFire SoC FPGA System Services User Guide.

If the System Controller Suspended Mode is disabled, it increases vulnerability to radiation single event effects (SEEs) in the System Controller.

The following table lists the programming support when System Controller Suspend Mode is enabled or disabled.

When the system controller is forced from suspend mode by asserting JTAG_TRSTB = 1, the outputs of the PF_INIT_MONITOR macro is forced = 0. This macro is often used for resetting the user logic design, so the appropriate user design considerations must be made for this operational case. See PolarFire FPGA and PolarFire SoC FPGA Power-Up and Resets User Guide for information about the usage of PF_INIT_MONITOR IP.