5.1 Transceiver Power Reduction Recommendations

The PolarFire device has options to reduce the power of the Transceiver PMA and the associated DFE calibration block. The following options are available to reduce the power consumption of the transceiver PMA as well as the DFE calibration block within the PCIESS and transceiver PCS blocks.

  • Disabling DFE and EM blocks, when CDR mode is used during normal operation
  • Disabling EM block (PDEM = 1'b0), when DFE mode is used during normal operation
  • Disabling the Calibration clock (DFE_CAL_CEN = 1'b0), when either PDDFE = 1'b1 or PDEM = 1'b1
    Important: These settings must be restored before any DFE/CDR calibration or eye monitor functions can be performed.
  • Modifying the CTLE Drive settings from the default of 0x2:
    • For setting 0x1, the estimated power reduction is by 1.5 mW.
    • For setting 0x3 (only for Revision F), the estimate power increases by 3.75 mW (3.93 mW when used with VDDA = 1.05V).
    • For PDDFE=1'b1 and PDEM = 1'b1, the Transceiver PMA power can be reduced further by setting CSENT[3:1]_DFEEM = 0x0.
  • Reduce the Tx amplitude:
    • The Tx amplitude must be large enough to transmit the required data and withstand cross-talk from other lanes, as much as possible. Additional amplitude beyond this optimal limit only increases power, noise, and cross-talk in the system.
    • De-emphasis must be used to improve the performance of the system by removing high frequency content that must be transferred across the backplane. Modifying de-emphasis parameters has no effect on the overall Transceiver power.
    • Examples of power reduction from the base of 88 mW at 6.875 Gbps for 1000 mV peak-peak amplitude settings are:
    Table 5-1. Example Settings
    Serial NumberTX Amplitude (mV)pk-pk (mW)
    1100088
    280081
    360074
    440067
    520060
  • Disable the TxPLL auxiliary clock:
    • If the auxiliary clock from the PLL is not needed, it must be disabled by setting TXPLL_AUXDIVPD/EXTPLL_AUXDIVPD = 1'b1. This setting saves the significant power on VDD rail.
    • Some functions within the Serial subsystem require the auxiliary clock output to be enabled. The main function known to require this function to be enabled is the jitter attenuator function.