3.3 M.2 Connector Pin Specification
The following table provides details on the interface between the M.2 connector and the WILCS02UE module.
| M.2 Pin Number | M.2 Pin Name | M.2 Connector Pin Description | WILCS02UE Module Pin Description | WILCS02UE Module Pin Number |
|---|---|---|---|---|
| 1 | GND | GND | — | GND |
| 3 | USB_D+ | USB differential data-positive | PTA_WLAN_ACTIVE | Pin 5 |
| 5 | USB_D- | USB differential data-negative | PTA_BT_PRIO | Pin 6 |
| 7 | GND | GND | — | GND |
| 9 | SDIO_CLK/SYSCLK(I)(0/1.8V) | SDIO clock input | SD_CLK/UART1_RX | Pin 19 |
| 11 | SDIO_CMD(I/O)(0/1.8V) | SDIO command line | SD_CMD/SCK1 | Pin 18 |
| 13 | SDIO_DATA0(I/O)(0/1.8V) | SDIO data line 0 | SD_DATA0/SDO1 | Pin 17 |
| 15 | SDIO_DATA1(I/O)(0/1.8V) | SDIO data line 1 |
SD_DATA1/CS1 | Pin 16 |
| 17 | SDIO_DATA2(I/O)(0/1.8V) | SDIO data line 2 | SD_DATA2/SDI1 | Pin 15 |
| 19 | SDIO_DATA3(I/O)(0/1.8V) | SDIO data line 3 | SD_DATA3/UART1_TX | Pin 14 |
| 21 | SDIO_WAKE# (O)(0/1.8V) | Wake-up host (output) | INTOUT | Pin 13 |
| 23 | SDIO_RESET#/TX_BLANKING (I)(0/1.8V) | — | — | — |
| 25 | ADD-IN CARD KEY E | |||
| 27 | ||||
| 29 | ||||
| 31 | ||||
| 33 | GND | — | — | GND |
| 35 | PERp0 | — | — | — |
| 37 | PERn0 | — | — | — |
| 39 | GND | — | — | GND |
| 41 | PETp0 | — | — | — |
| 43 | PETn0 | — | — | — |
| 45 | GND | — | — | GND |
| 47 | REFCLKp0 | — | — | — |
| 49 | REFCLKn0 | — | — | — |
| 51 | GND | — | — | GND |
| 53 | CLKREQ0# (I/O)(0/1.8V/3.3V) | — | — | — |
| 55 | PEWAKE0# (I/O)(0/1.8V/3.3V) | — | — | — |
| 57 | GND | — | — | GND |
| 59 | RESERVED/PERp1 | — | — | — |
| 61 | RESERVED/PERn1 | — | — | — |
| 63 | GND | — | — | GND |
| 65 | RESERVED/PETp1 | — | — | — |
| 67 | RESERVED/PETn1 | — | — | — |
| 69 | GND | — | — | GND |
| 71 | RESERVED/REFCLKp1 | — | — | — |
| 73 | RESERVED/REFCLKn1 | — | — | — |
| 75 | GND | — | — | GND |
| 2 | 3.3V | 3.3V DC power | VDD | Pin 20 |
| 4 | 3.3V | 3.3V DC power | VDD | Pin 20 |
| 6 | LED_1# (O)(OD) | — | — | — |
| 8 | PCM_CLK/I2S_SCK (I/O)(0/1.8V) | — | — | — |
| 10 | PCM_SYNC/I2S_WS (I/O)(0/1.8V) | — | — | — |
| 12 | PCM_OUT/I2S_SD_OUT (O)(0/1.8V) | — | — | — |
| 14 | PCM_IN/I2S_SD_IN (I)(0/1.8V) | — | — | — |
| 16 | LED_2# (O)(OD) | — | — | — |
| 18 | VIO_CFG (O) | — | — | — |
| 20 | UART_WAKE# (O)(0/3.3V) | Wake-up Host (output) | INTOUT | Pin 13 |
| 22 | UART_TXD (O)(0/1.8V) | UART Serial Data Output | SD_DATA3/UART1_TX | Pin 14 |
| 24 | ADD-IN CARD KEY E | |||
| 26 | ||||
| 28 | ||||
| 30 | ||||
| 32 | UART_RXD (I)(0/1.8V) | UART Serial Data Input | SD_CLK/UART1_RX | Pin 19 |
| 34 | UART_RTS (O)(0/1.8V) | UART Request To Send (output) | SD_DATA2/SDI1 | Pin 15 |
| 36 | UART_CTS (I)(0/1.8V) | UART Clear To Send (input) |
SD_DATA1/CS1 | Pin 16 |
| 38 | VENDOR DEFINED | Mode selection 1/DFU 1 | DFU_RX/STRAP1 | Pin 10 |
| 40 | VENDOR DEFINED | WAKE (input) | Reserved | Pin 11 |
| 42 | VENDOR DEFINED | Mode selection 2/DFU 2 | DFU_TX/STRAP2 | Pin 26 |
| 44 | COEX3 (I/O)(0/1.8V) | PTA_BT_PRIO (input) | PTA_BT_PRIO | Pin 6 |
| 46 | COEX_TXD (O)(0/1.8V) | PTA_WLAN_Active (output) | PTA_WLAN_Active | Pin 5 |
| 48 | COEX_RXD (I)(0/1.8V) | PTA_BT_Active (input) | RTCC_OSC_IN/PTA_BT_ACTIVE | Pin 21 |
| 50 | SUSCLK(I)(0/1.8V/3.3V) | 32.768 kHz clock input from M.2 host platform | RTCC_OSC_IN/PTA_BT_ACTIVE | Pin 21 |
| 52 | PERST0# (I)(0/1.8V/3.3V) | — | — | — |
| 54 | W_DISABLE2# (I)(0/1.8V/3.3V) | Master Clear (input) | MCLR | Pin 4 |
| 56 | W_DISABLE1# (I)(0/1.8V/3.3V) | — | — | — |
| 58 | I2C_DATA (I/O)(0/1.8V) | I2C data | Reserved | Pin 3 |
| 60 | I2C_CLK (I)(0/1.8V) | I2C clock | Reserved | Pin 2 |
| 62 | ALERT# (O)(0/1.8V) | Wake-up host (output) | INTOUT | Pin 13 |
| 64 | VIO1.8V | — | — | — |
| 66 | UIM_SWP/PERST1# | — | — | — |
| 68 | UIM_POWER_SNK/CLKREQ1# | — | — | — |
| 70 | UIM_POWER_SRC/GPIO_1/PEWAKE1# | — | — | — |
| 72 | 3.3V | 3.3V DC power | VDD | Pin 20 |
| 74 | 3.3V | 3.3V DC power | VDD | Pin 20 |
|
Note: The PTA functionality is not supported
while using the RTCC Oscillator.
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