The Write Enable Latch (WEL) bit of the STATUS register must be set to logic ‘1’
prior to each Write STATUS Register (WRSR) and Write to Memory Array
(WRITE) instruction. This is accomplished by sending a
WREN (06h) instruction to the AT25080B/AT25160B. First, the CS pin is driven low to
select the device, and then a WREN instruction is clocked in on the SI
pin. After that, the CS pin can be driven high, and the WEL bit
will be updated in the STATUS register to logic ‘1’. The device will
power up in the Write Disable state (WEL = 0).Figure 6-2. WREN Timing
DS20006244C
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