3.2.2 Main Configurations and Control

The following figure shows the power main configuration and control.

Figure 3-10. Processor Main Configuration and Control
Table 3-2. Processor Main Configuration and Control Signals
Pin NameTypeSignal Description
XINInputMain Clock Oscillator input
XOUTOutputMain Clock Oscillator output
XIN32InputSlow Clock Oscillator input
XOUT32OutputSlow Clock Oscillator output
SHDNOutputEnable or disable an external power supply circuit in Low-Power modes
WKUP0InputEvent detection used to wake up the processor from Shutdown state
JTAGSELInputJTAG boundary scan (1L) or Embedded ICE (0L) selection pin
TCKInputICE and JTAG Test Clock
TDIInputICE and JTAG Test Data In
TDOOutputICE and JTAG Test Data Out
TMSInputICE and JTAG Test Mode Select
RTCKOutputICE and JTAG Return Test Clock
NRSTInputExternal Reset Input
TSTInputTest Mode Select
ADVREFPAnalog InputPositive reference voltage
ADREFNAnalog InputNegative reference voltage
DDRM_CALAnalog InputSDRAM Controller Calibration Input
DDR_ZQAnalog Calibration for DQ drive and ODT
HHSDMAAnalogUSB Host Port A High Speed Data -
HHSDPAAnalogUSB Host Port A High Speed Data +
HHSDMBAnalogUSB Host Port B High Speed Data -
HHSDPBAnalogUSB Host Port B High Speed Data +
HHSDMCAnalogUSB Host Port C High Speed Data -
HHSDPCAnalogUSB Host Port C High Speed Data +
HHSRTUNEInputUSB external tunning
MIPI_CLKPOMIPI D-PHY Differential Output Clock Lane +
MIPI_CLKNOMIPI D-PHY Differential Output Clock Lane -
MIPI_DPxI/OMIPI D-PHY Differential Output Data Lane + [3:0]
MIPI_DNxI/OMIPI D-PHY Differential Output Data Lane - [3:0]
MIPI_REXTAnalog InputCalibration Reference Resistor
AUDIO_CLKOutputAudio Programmable Clock Output
DDR_VREFAnalog InputI/O Reference Voltage