3.2.2 Main Configurations and Control

The following figure shows the power main configuration and control.

Figure 3-10. Processor Main Configuration and Control

Table 3-2. Processor Main Configuration and Control Signals
Pin Name	Type	Signal Description
XIN	Input	Main Clock Oscillator input
XOUT	Output	Main Clock Oscillator output
XIN32	Input	Slow Clock Oscillator input
XOUT32	Output	Slow Clock Oscillator output
SHDN	Output	Enable or disable an external power supply circuit in Low-Power modes
WKUP0	Input	Event detection used to wake up the processor from Shutdown state
JTAGSEL	Input	JTAG boundary scan (1L) or Embedded ICE (0L) selection pin
TCK	Input	ICE and JTAG Test Clock
TDI	Input	ICE and JTAG Test Data In
TDO	Output	ICE and JTAG Test Data Out
TMS	Input	ICE and JTAG Test Mode Select
RTCK	Output	ICE and JTAG Return Test Clock
NRST	Input	External Reset Input
TST	Input	Test Mode Select
ADVREFP	Analog Input	Positive reference voltage
ADREFN	Analog Input	Negative reference voltage
DDRM_CAL	Analog Input	SDRAM Controller Calibration Input
DDR_ZQ	Analog	Calibration for DQ drive and ODT
HHSDMA	Analog	USB Host Port A High Speed Data -
HHSDPA	Analog	USB Host Port A High Speed Data +
HHSDMB	Analog	USB Host Port B High Speed Data -
HHSDPB	Analog	USB Host Port B High Speed Data +
HHSDMC	Analog	USB Host Port C High Speed Data -
HHSDPC	Analog	USB Host Port C High Speed Data +
HHSRTUNE	Input	USB external tunning
MIPI_CLKP	O	MIPI D-PHY Differential Output Clock Lane +
MIPI_CLKN	O	MIPI D-PHY Differential Output Clock Lane -
MIPI_DPx	I/O	MIPI D-PHY Differential Output Data Lane + [3:0]
MIPI_DNx	I/O	MIPI D-PHY Differential Output Data Lane - [3:0]
MIPI_REXT	Analog Input	Calibration Reference Resistor
AUDIO_CLK	Output	Audio Programmable Clock Output
DDR_VREF	Analog Input	I/O Reference Voltage