4 DDR2 SDRAM Features

The SAM9X75 SiP is available with a 512-Mbit DDR2 SDRAM memory option.

For power consumption, electrical characteristics and memory timings, refer to the manufacturer’s documentation listed in Reference Documents.

• Power Supply: DDRM_VDD = 1.8V ±0.1V
• Double Data Rate architecture: two data transfers per clock cycle
• CAS latency: 3
• Burst length: 8
• Bidirectional, differential data strobes (DQS and DQSN) are transmitted/received with data
• Edge-aligned with read data and center-aligned with write data
• DLL aligns DQ and DQS transitions with clock
• Differential clock inputs (CLK and CLKN)
• Data masks (DM) for write data
• Commands entered on each positive CLK edge; data and data mask referenced to both edges of DQS
• Auto-Refresh and Self-Refresh modes
• Precharged power-down and active power-down
• Write data mask
• Write latency = read latency - 1 (WL = RL - 1)