3.1.1 Device Reset Pad (DEVRST_N)

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DEVRST_N or device reset, is powered through the dedicated I/O bank. The DEVRST_N assertion results in full re-initialization of the device, including the loading of user configuration data to PCIe, transceivers, and the re-initialization of MSS, fabric LSRAMs, and µSRAMs.

The DEVRST_N may be pulled low by an external source in order to schedule a full device reset and reboot. This is not an asynchronous reset, but asserts a Non-Maskable Interrupt (NMI) to the processor in the system controller, which then starts the watchdog timer to schedule an unstoppable device reset, to be asserted after the firmware has disabled I/Os and fully executed a safe power-down of the fabric.

Important: During the assertion of DEVRST_N, the state of I/Os (Input/Output pins) in PolarFire family FPGAs enter a high-impedance state (tristated).

For designing a robust system, users may use the dedicated DEVRST_N pin or a general-purpose reset signal using any GPIO/HSIO as a global system reset. For the following cases, the users can use the DEVRST_N as a warm reset for the device:

User design modifies auto-initialized fabric RAMs or PCIe configuration during operation.
User design is using transceivers or UserCrypto.

In the case of PCIe, for resetting the PCIESS, use the PCIe_x_PERST_N input. The PCIe_x_PERST_N is a sideband reset input. For resetting PCIESS using drivers, use hot reset (in-band reset).

A hot reset is propagated in-band from one link neighbor to another by sending several TS1 (training sequence 1 packets) with bit0 of symbol 5 asserted. These TS1 are sent on all the lanes. When sent, the Tx and Rx of hot reset end up in detect LTSSM (link training state machine) state. Hot reset is initiated by software by setting the secondary bus reset bit in the Root Port's Bridge control configuration register.

For all other use cases, it is recommended to use a general-purpose reset signal using any GPIO, HSIO, or I/O because they take much shorter time for design to come out of reset.

If the dedicated DEVRST_N is not used for warm resets, the DEVRST_N pin must be configured using one of the following methods:

Drive the signal with a POR chip or an external device and keep the DEVRST_N asserted till the system/clocks are stable and the chip is properly powered up.
Connect DEVRST_N to VDDI3 through a 1 kΩ resistor per pin without sharing with any other pins.
- In this case, the user needs to ensure that all clocks going to the device are stable before the user design is released from power-on reset. The details of the minimum time taken for the fabric design to be activated after power-on is specified in the Power-Up To Functional Timing section of PolarFire FPGA Datasheet , RT PolarFire FPGA Datasheet , PolarFire SoC FPGA Datasheet , or RT PolarFire SoC FPGA Datasheet .