7 Revision History

• Added information that the HSIO/GPIO banks are tri-stated if the power goes below 0.85V in the Power-On section.
• Updated information about latch behavior in the following sections:
  • PolarFire Initialization Monitor
  • PolarFire SoC Initialization Monitor
  • System Controller Suspend Mode

• Updated the lead sentence for Table in Introduction for better clarity.
• Removed the sentence that mentioned eNVM support for SECDED in Embedded Non-Volatile Memory (eNVM) (For PolarFire SoC and RT PolarFire SoC FPGA Only).
• Updated the Important note in Device Programming and System Services to mention PolarFire® SoC as a supported device family.

• Updated the document for RT PolarFire SoC support. The changes are made throughout the document.
• Updated the calibration related information in the Device Boot and Design and Memory Initialization sections.
• Updated that the U_MSS_BOOTADDR register is set by the System Controller in the Idle Boot and Non-Secure Boot sections.
• Updated HSIO/GPIO Bank Initialization for the following:
  • Added a note that BANK 3 I/O does not calibrate.
  • Added details about bank calibration settings.
  • Expanded details on the impact of bank voltages, ramp time and auto calibration time out settings to calibration time.
  • Updated the suggested user monitoring of calibration process.
  • Added calibration subsystem configuration recommendations.
• Updated I/O Recalibration to enhance clarity on I/O calibration and how to use it.
• Renamed the I/O Editor section to I/O Recalibration Opt-out and enhanced information about I/O editor options that support I/O calibration.
• Added a note in Device Reset Pad (DEVRST_N).
• Updated the description of the FABRIC_RESET signal in Table 4-2 in MSS E51 Processor Watchdog Timeout Reset.
• Added a paragraph at the end in MSS E51 Processor Watchdog Timeout Reset.

• Updated the GPIO_RESET description in MSS E51 Processor Watchdog Timeout Reset to clearly specify that the fabric asserts the MSS GPIO soft reset.

• Changed the document title to “PolarFire Family Power-Up and Resets User Guide”.
• Removed information about UIC.
• Updated PF_INIT_MONITOR and PFSoC_INIT_MONITOR configurator GUI screenshots to match with the latest core. See PolarFire Initialization Monitor and PolarFire SoC Initialization Monitor.
• Updated information about PLL_POWERDOWN_B control of CCC when using feedback modes. See User Reset Generation Schemes.

• Added information about Broadcast instructions to initialize RAMs to zeros and updated information about SPI Clock Divider. See How To Set Up Design and Memory Initialization
• Added information about how to generate Design Initialization Data and Memory report. See Figure   2
• Updated information about recalibration operation. See I/O Recalibration

• The tamper voltage monitors do not require latching when system controller suspend mode is enabled. Removed the information about latching of Tamper flags when System Controller Suspend Mode is enabled. See Design and Memory Initialization
• Information about SPI part for PolarFire FPGA and for PolarFire SoC FPGA was added. See How To Set Up Design and Memory Initialization
• Information about fixed delay when device boot starts was updated. See Power-On
• Information about PUFT timing data report was updated. See Power-Up To Functional (PUFT) Timing Data Report
• Information about sNVM was updated to include the Initialize sNVM Master Key feature. See Figure   4
• Information about eNVM was updated to include the digest calculation feature. See Figure   3

• Added information about latching of tamper flag outputs when system controller suspend mode is enabled. See Design and Memory Initialization
• Updated information about PF_INIT_MONITOR operation and use model when system controller suspend mode is enabled. See PolarFire Initialization Monitor and PolarFire SoC Initialization Monitor
• Added information about CORERESET_PF IP. See PolarFire and RT PolarFire FPGA Resets and PolarFire SoC and RT PolarFire SoC FPGA Resets. No change in functionality
• Added information about System Controller Suspend Mode. See System Controller Suspend Mode
• Updated the reset block diagrams for the RESET_DEVICE signal. See Figure   1 and Figure   1
• Updated information about programmable delay. See Power-On

The following is a summary of changes in the revision B of the document:

• UG0725: PolarFire FPGA Device Power-up and Reset User Guide
• PolarFire SoC FPGA Power-up and Reset User Guide

The revision history tables of both the user guides are retained here for future reference. For information, see Table   1 and Table   2.

The following is a summary of changes in the revision A of the document:

• Information about the transceiver initialization time was added. See Transceiver Initialization.
• Information about the PCIe initialization time was added. See PCIe Initialization.
• Information about IO re-calibration was added. See IO Recalibration.
• Document formatted to Microchip template. Document number is changed from 50200890 to DS60001676.

• Information about Power-up Function Timing (PUFT) timing parameter for SUSPEND_EN was added. See Design and Memory Initialization.
• Information about How To Set Up Design and Memory Initialization was updated.

• Information about re-calibration was added. See IO Recalibration.
• Information about the transceiver initialization time was added. See Transceiver Initialization.
• Information about the PCIe initialization time was added. See PCIe Initialization.

• Information about Design and Memory Initialization was updated.
• Information about ramp-up time was added. See HSIO/GPIO Bank Initialization.
• Information about low-speed IO calibration was added. See HSIO/GPIO Bank Initialization.

• Updated the document for Libero SoC v12.0.
• Updated the steps to initialize the fabric RAMs, see How To Set Up Design and Memory Initialization.

• Updated the document for Libero SoC PolarFire v2.1.
• Updated Device Boot.
• Updated Design and Memory Initialization.
• Updated How To Set Up Design and Memory Initialization.
• Updated HSIO/GPIO Bank Initialization.
• Updated Transceiver Initialization.
• Updated State of Blocks During Power-Up.

• Updated the screen shots as per the Libero SoC PolarFire v2.0 release through out the document.
• A note about SPI Slave Programming mode is deleted from the Design and Memory Initialization and the section is edited to add the usage of PolarFire Initialization Monitor.
• Added μPROM and External SPI Flash sections (see μPROM and External SPI Flash, Edited HSIO/GPIO Bank Initialization to describe BANK_#_CALIB_STATUS and BANK_#_VDDI_STATUS signals.
• A note is added in Power-Up to Functional Time to give a reference to PolarFire FPGA Datasheet.
• Deleted the Top-Level Device Power-Up figure from the Power-Up.
• Deleted GPIO_ACTIVE and HSIO_ACTIVE pins and added BANK_#_CALIB_STATUS and BANK_#_VDDI_STATUS pins in Simplified Block Diagram of Resets figure.
• Recommendation on device reset usage was added in DEVRST_N.
• Power-up To Functional Time figure was updated.

• The document was updated to include features and enhancements introduced in the Libero SoC PolarFire v1.1 SP1 release.
• Information about the use case of PolarFire Initialization Monitor was added. For more information, see User Reset Generation Scheme.

The following is a summary of changes made in this revision.

• Information about ramp-up time was added. See HSIO/GPIO Bank Initialization.
• Information about low-speed IO calibration was added. See HSIO/GPIO Bank Initialization.
• Information about MSS Pre-Boot (For PolarFire SoC and RT PolarFire SoC FPGA Only) and MSS User Boot (For PolarFire SoC and RT PolarFire SoC FPGA Only) was added.
• Information about User Reset Generation Scheme was updated.

The following is a summary of changes made in this revision.

• Information about Design and Memory Initialization was updated.
• Information about How To Set Up Design and Memory Initialization was added.
• Information about User Reset Generation Scheme was added.