2.2.1 Core10GMAC
(Ask a Question)Core10GMAC is configured for 10GBASE-R mode with a core data width of 32 bits. Core data width is the width of the data path connected to the transceiver interface. The system data width is the width of the interface to the user logic, and is configured as 64 bits. (In this demo, the FiFo_wrapper_top module provides this interface).
The Tx and Rx Pause features are disabled, and both the MAC TX FIFO depth and MAC RX FIFO depth are set to 256.
The Core10GMAC IP is configured using the CoreABC soft processor. The following table lists Core10GMAC configuration for the demo design.
| Register | Address | Offset | Bit | Binary Value |
|---|---|---|---|---|
| MAC Tx Config Register | (0xA) | 0x3 | cfg_sys_mac_tx_en | 1 |
| 0x4 | sys_mac_tx_fcs_ins | 1 | ||
| MAC Rx Config Register | (0xB) | 0x0 | mac_rx_fcs_remove | 1 |
| 0x3 | cfg_sys_mac_rx_en | 1 |
For more information about the features and registers of Core10GMAC, see Core10GMAC User Guide.