1.1.2 Phase Tracking Mode
(Ask a Question)If the frequency error between FIN and FFB increases beyond 5000 ppm, FLOCK is reset to "0" and the loop exits phase tracking mode and reenters frequency tracking mode. The loop remains in this stage till the frequency lock is achieved back.
Once the PLL is in phase tracking mode, it remains in this mode for DELAYK feedback clock cycles. It spends first DELAYK/2 cycles times in coarse phase tracking mode and the remaining half in fine phase tracking mode. At this point, PHASE_LOCK will be set to "1" and TRANSITION will be set to "0", indicating the PLL is locked to phase and frequency.
When PHASE_LOCK is "1", the PLL will not track high-frequency offset signals and its output frequency remains relatively stable. PLL only exits this state if the frequency lock is lost.
The following figures show the block diagram of Jitter Attenuating PLL and register information.
The following table lists the register details.
| SCB Register | DPLL Parameter | Description |
|---|---|---|
| TXPLL_JA_1 | TXPLL_JA_DIVFIN | Integer divider for FIN |
| TXPLL_JA_DIVFFB | Integer divider for FFB | |
| TXPLL_JA_2 | TXPLL_JA_SYNCCNTMAX | Maximum count values to determine frequency match |
| TXPLL_JA_3 | TXPLL_JA_CNTOFFSET | OFFSET value used for frequency tracking |
| TXPLL_JA_TARGETCNT | If pulse count between FIN and FFB are less than TARGETCNT then the frequency detector declares frequency match | |
| TXPLL_JA_4 | TXPLL_JA_OTDLY | Time duration to delay the FFB pulses when transitioning from frequency tracking to phase tracking stage to avoid glitches in FLOCK signal |
| TXPLL_JA_FMI | M gain for frequency integral control | |
| TXPLL_JA_FKI | K gain for frequency integral control | |
| TXPLL_JA_5 | TXPLL_JA_PMP1 | M gain for Proportional phase comparison loop course setting |
| TXPLL_JA_PMP2 | M gain for Proportional phase comparison loop fine setting | |
| TXPLL_JA_PMI1 | M gain for Integral phase comparison loop course setting | |
| TXPLL_JA_PMI2 | M gain for Integral phase comparison loop fine setting | |
| TXPLL_JA_6 | TXPLL_JA_PKP1 | K gain for Proportional phase comparison loop course setting |
| TXPLL_JA_PKP2 | K gain for Proportional phase comparison loop fine setting | |
| TXPLL_JA_PKI1 | K gain for Integral phase comparison loop course setting | |
| TXPLL_JA_PKI2 | K gain for Integral phase comparison loop fine setting | |
| TXPLL_JA_7 | TXPLL_JA_DELAYK | Phase comparison loop initially settles using PKP1 and PKI1 (course settling) parameters, and switch over to PKP2 and PKI2 (fine settling) parameters. DELAYK FFB pulses after phase comparison loop takes over (OTDLY + DELAYK FFB pulses after initial frequency lock). |
| TXPLL_JA_FDONLY | 1'b1: Frequency + Phase control 1'b0: Frequency control only | |
| TXPLL_JA_ONTARGETOV | 1'b1: Normal Operation 1'b0: Diagnostic mode | |
| TXPLL_JA_PROGRAM | 1'b1: Normal Operation 1'b0: Diagnostic mode | |
| TXPLL_JA_8 | TXPLL_JA_FRAC_PRESET | When PRESET_EN: 1'b1, FRAC is equal to TXPLL_JA_FRAC_PRESET |
| TXPLL_JA_PRESET_EN | Load preset INT and FRAC values into DPLL | |
| TXPLL_JA_HOLD | Hold output state of DPLL 1'b1: Hold, PLL will not phase lock in this state 1'b0: Normal operation | |
| TXPLL_JA_9 | TXPLL_JA_INT_PRESET | When PRESET_EN: 1'b1, INT is equal to TXPLL_JA_INT_PRESET |
| TXPLL_JA_INT_PD_OUT | Integer bits of phase detector output | |
| TXPLL_JA_10 | TXPLL_JA_PHASE_LOCK | 1'b1: DPLL is in fine tune phase tracking mode 1'b0: DPLL is in coarse tune phase tracking mode |
| TXPLL_JA_FLOCK | 1'b1: DPLL has achieved frequency lock 1'b0: DPLL has not achieved frequency lock | |
| TXPLL_JA_FRAC_PD_OUT | Fractional bits of phase detector output | |
| TXPLL_JA_RST | TXPLL_JA_RESET | 1'b1: DPLL reset asserted 1'b0: DPLL reset deasserted |
| TXPLL_JA_RESET_FFB_OVERRIDE | 1'b0: Disables DPLL override signal for feedback clock domain reset signal. 1'b0: Enables DPLL override signal for feedback clock domain reset signal. | |
| TXPLL_JA_RESET_FFB_EXT | 1'b0: DPLL reset for feedback clock domain is de-asserted 1'b1: DPLL reset for feedback clock domain is asserted | |
| TXPLL_JA_RESET_FIN_OVERRIDE | 1'b0: Disables DPLL override signal for input clock domain signal 1'b1: Enables DPLL override signal for input clock domain reset signal | |
| TXPLL_JA_RESET_FIN_EXT | Reset for input clock domain when RESET_FIN_OVERRIDE is 1'b1 | |
| TXPLL_JA_RESET_CLKS_OVERRIDE | 1'b0: Disables DPLL override signal for PLL Sync clock domain reset signal 1'b1: Enables DPLL override signal for PLL Sync clock domain reset signal | |
| TXPLL_JA_RESET_CLKS_EXT | Reset for PLL Sync Clock Domain when RESET_CLKS_OVERRIDE is 1'b1 |