3.3 Event Driven SleepWalking Example on PIC32CM PL10

In the SleepWalking implementation, the application takes advantage of the Event System. The Real-Time Counter (RTC) will automatically start the ADC conversion using the Event System of the chip without any CPU intervention.

The application scenario is explained in the following steps:

1. The Real-Time Counter (RTC) is configured as an Event Generator to generate a periodic event (~100 ms using OSC1K 1.024 kHz clock source) to Timer/Counter 0 (TC0) and Timer/Counter 1 (TC1) through the PIC32CM PL10 Event System (EVSYS) Channel 0.
2. TC0 generates a ~12 ms Pulse-Width Modulation (PWM) pulse on PA00 to power the ambient light sensor.
3. TC1 provides an Analog-to-Digital Converter (ADC) pacing timer with ~10 ms delay for sensor warm-up. When TC1 overflows, it triggers the ADC conversion through EVSYS Channel 1.
4. The ADC acknowledges the event from TC1 and starts a conversion. The ADC Result Ready (RESRDY) event is routed to Timer/Counter 2 (TC2) through EVSYS Channel 2.
5. The Direct Memory Access (DMA) controller moves the ADC result from the ADC Result register to a circular buffer (20 entries) in RAM.
6. TC2 generates an overflow interrupt (~4.9 µs after ADC conversion) to wake up the CPU to Active mode.
7. The CPU checks if any buffered samples exceed the window threshold (upper threshold = 1024) and transmits data through Universal Asynchronous Receiver/Transmitter (UART) at 460800 baud only when the threshold is crossed. The baud rate is increased from 230400 so that the time spent sending the light measurements to the terminal is minimized, and the average current consumption is reduced.
8. The CPU returns to Standby mode. The entire sampling pipeline (RTC → EVSYS → TC0/TC1 → ADC → DMA) runs autonomously without CPU involvement.

The CPU and RAM will not wake up when SleepWalking-supported peripherals perform their tasks, unless the CPU needs to perform an operation. This autonomous operation is the key to SleepWalking's power efficiency, where the CPU remains in deep Standby while the Event System orchestrates peripheral-to-peripheral communication.

The power consumption for the SleepWalking sequence was measured using the Atmel Power Debugger and captured with the MPLAB Data Visualizer across three operating conditions, as shown in the following figures.

Under normal steady-state operation, when the ambient light reading remains below the detection threshold, the Power Analysis reports an average current of ~9.91 µA, with a minimum of 2.1 µA and brief peaks of up to 91.9 µA during the autonomous ADC sampling bursts every 100 ms. This represents a 99.8% reduction compared to the 6.18 mA Active mode baseline. The regular spike pattern confirms that the Event System pipeline is sampling reliably every 100 ms entirely without CPU involvement.

When the brightness threshold is crossed and the CPU wakes to transmit data through UART, the average current rises to ~159 µA, with peaks up to 1.66 mA during transmission events. Despite the challenging conditions, which involve the combined cost of the autonomous sampling pipeline and periodic CPU activity, the implementation successfully achieves a 97.4% reduction from the Active mode baseline. The irregular taller spikes visible in the waveform correspond to the infrequent CPU wake events triggered only when actionable data is present, demonstrating the threshold-gated wake-up paradigm in action.

The third measurement provides a high-resolution view of the true hardware Standby baseline between sampling events, a 78.7 ms capture window isolated between two successive CPU wake-up transitions. During this deep Standby interval, the device draws an average of just ~2.39 µA, with a noise floor minimum near zero. This confirms that the SleepWalking architecture achieves near-ideal Standby current between sampling cycles, with all clocks halted and no peripheral activity consuming power. This baseline is the fundamental lower bound of the implementation's power profile and validates the efficiency of the on-demand clocking mechanism described in the Regulator Selection During SleepWalking section.

Together, the three measurements provide a comprehensive overview: the system idles at 2.39 µA between samples, rises briefly to sub-100 µA spikes during autonomous peripheral activity, and reaches 159 µA only on the rare occasions when the CPU wakes for UART transmission. The resulting time-averaged current of ~9.91 µA under typical operating conditions represents a 99.8% reduction from the Active mode baseline of 6.18 mA.