40.7.3 ADCON2

ADC Control Register 2
Note:
  1. To correctly calculate an average, the number of samples (set in ADRPT) must be 2CRS.
  2. CRS = ‘b111 and ‘b000 are reserved.
  3. This bit is cleared by hardware when the accumulator operation is complete; depending on oscillator selections, the delay may be many instructions.
  4. See the Computation Operation section for full mode descriptions.
Name: ADCON2
Address: 0x3F5

Bit 76543210 
 PSISCRS[2:0]ACLRMD[2:0] 
Access R/WR/WR/WR/WR/W/HCR/WR/WR/W 
Reset 00000000 

Bit 7 – PSIS ADC Previous Sample Input Select

ValueDescription
1 ADFLTR is transferred to ADPREV at start-of-conversion
0 ADRES is transferred to ADPREV at start-of-conversion

Bits 6:4 – CRS[2:0] ADC Accumulated Calculation Right Shift Select

ValueNameDescription
1 to 6 MD =‘b100 Low-pass filter time constant is 2CRS, filter gain is 1:1(2)
1 to 6 MD =‘b011 to ‘b001 The accumulated value is right-shifted by CRS (divided by 2CRS)(1,2)
x MD =‘b000 These bits are ignored

Bit 3 – ACLR  A/D Accumulator Clear Command(3)

ValueDescription
1 The ADACC and ADCNT registers and the AOV bit are cleared
0 Clearing action is complete (or not started)

Bits 2:0 – MD[2:0]  ADC Operating Mode Selection(4)

ValueDescription
111-101 Reserved
100 Low-Pass Filter mode
011 Burst Average mode
010 Average mode
001 Accumulate mode
000 Basic (Legacy) mode
To correctly calculate an average, the number of samples (set in ADRPT) must be 2CRS. CRS = ‘b111 and ‘b000 are reserved. This bit is cleared by hardware when the accumulator operation is complete; depending on oscillator selections, the delay may be many instructions. See the Computation Operation section for full mode descriptions.