30.9.2 PWMxCLK
| Name: | PWMxCLK |
| Address: | 0x461,0x470,0x47F |
PWMx Clock Source
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| CLK[3:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | |||||
| Reset | 0 | 0 | 0 | 0 | |||||
Bits 3:0 – CLK[3:0] PWM Clock Source Select
| CLK | Source | Operates in sleep |
|---|---|---|
1111 | Reserved | N/A |
1110 | CLC4_OUT | Yes(1) |
1101 | CLC3_OUT | Yes(1) |
1100 | CLC2_OUT | Yes(1) |
1011 | CLC1_OUT | Yes(1) |
1010 | NCO1_OUT | Yes(1) |
1001 | CLKREF | Yes(1) |
1000 | EXTOSC | Yes |
0111 | SOSC | Yes |
0110 | MFINTOSC (32 kHz) | Yes |
0101 | MFINTOSC (500 kHz) | Yes |
0100 | LFINTOSC | Yes |
0011 | HFINTOSC | Yes |
0010 | FOSC | No |
0001 | PWMIN1PPS | Yes(1) |
0000 | PWMIN0PPS | Yes(1) |
|
Note: Operation
during Sleep is possible if the clock supplying the source
peripheral operates in Sleep.
| ||