4.2 Application Board Design

This section describes the application and reference board design for the ATA8510/15 and gives recommendations about optimizing the layout for the ATA8510/15 application.

The following figure shows the schematic of the ATA8510/15 application board. The application boards are delivered using the SPDT RF switch; no SAW is used and no antenna tuning is applied. The Ant1 pin of the application board is the 50Ω RF input and output. Table 4-14, Table 4-15 and Table 4-16 summarize the corresponding board populations for 315 MHz, 433.92 MHz and 868 MHz, respectively. The boards are manufactured using FR4 material with a PCB thickness of 1 mm.

The application board also provides the option of verifying the performance of RFIN_LB(HB) or RF_OUT directly without using the SPDT. The electrical characteristics in Electrical Characteristics are primarily measured using a matching network between either RFIN_LB or RFIN_HB and Ant2 (RXMode) or a matching network between RF_OUT and Ant1 (TXMode). This is shown for each parameter in the “Pin” column of the Electrical Characteristics table on Electrical Characteristics; for example, a “(1)” means that the sensitivity is measured at pin 1 RFIN_LB and that, if used, the insertion loss of the SPDT has to be added.

The matching networks of the receive path without using the SPDT is found in LNA and Mixer. In Power Setting and Matching to a 50Ω Load, the matching networks of the transmit path without the SPDT for 6 dBm, 10 dBm and 14 dBm output power are shown.

In SPDT RF Switch and Automatic Antenna Tuning, the matching networks for using the SPDT RF switch is explained in more detail. Optimized matching networks for 6 dBm, 10 dBm and 14 dBm transmit power with SPDT is also indicated there.

All matching networks are also available for the 915 MHz application in the sections referred to.

The layout of the application board is illustrated in the following figure.

For the layout illustrated in the preceding figure, the component diagram shows in the following figure.

The following items must be considered while designing a layout for the ATA8510/15 application board:

1. The decoupling capacitor of AVCC, C₁₂ must be placed as close as possible to pin 12 because, otherwise, the series inductance is too high and supply bypassing is no longer effective at high frequencies.
2. The decoupling capacitor of DVCC, C₁₄ must be placed as close as possible to pin 20. This decoupling capacitor must be connected directly to the DGND pin and ground layer using vias, as shown in Figure 4-22. Otherwise, the sensitivity of the receiver or the spurious performance of the transmitter may be worsened by the spurious clock emission of the integrated AVR.
3. The decoupling capacitor of VS_PA, C₁₁ must be placed as close as possible to pin 8, because, otherwise, the series inductance is too high and the power amplifier may not work correctly. An extra capacitor placed close to pin 8 (VS_PA) and another capacitor close to pin 13 (VS) is, therefore, needed.
4. The decoupling capacitor of VS, C₁₃ must be placed as close as possible to pin 13, because, otherwise, the series inductance is too high and supply bypassing is no longer effective at high frequencies.
5. Direct connection of the DGND pin to the exposed die pad must be avoided, and at least four vias must be placed under the exposed die pad. If this is not done, the isolation of the integrated AVR from the RF front end is worse. The exposed die pad is also the RF ground for receive and transmit operation and reduced sensitivity or output power may result from bad ground connection on the exposed die pad.
6. The crystal must be placed as close as possible to the IC to avoid extra capacitance on XTAL1 and XTAL2.
7. It is advisable to design the lines carrying the RF signal to be as short as possible and place the elements of the matching networks as close as possible to the IC (Ant1 to SPDT_ANT, RF_OUT to SPDT_TX and SPDT_RX to RFIN_LB/RFIN_HB).
8. If the antenna tuning feature is not used, the ANT_TUNE pin must remain open.
9. Avoid routing XTAL, AVCC and VS lines in parallel and close to each other over long distances; doing so reduces the coupling of the XTO signals to the supply voltage. Failing to do so may cause spurious receiver or transmitter emissions.
10. Avoid routing XTAL1 and XTAL2 lines in parallel and close to each other over long distances, to avoid a reduction of the XTO oscillation margin.
11. If using only one RFIN pin, it is advisable for the other RFIN to be connected to GND.
12. If the SPDT is not used, it is advisable to leave pins 3, 4 and 6 open.

The following tables show the bill of material of the application boards for 315 MHz, 433.92 MHz and 868.3 MHz applications. The required power supply for the application board is 3V. Connecting 5V to the ATA8510/15 PCB populated for 3V application destroys the IC. The power amplifier matching L₃ and C₉ is designed for 14 dBm transmit power. The SPDT is used for RXMode and TXMode. Components not mentioned in the following tables are not mounted.

The L₃ and C₉ component values optimized for a 6 dBm or a 10 dBm output power setting are found in RF_OUT Matching. Receive path matching is independent of the transmit path matching. As a result, the C₃, C₄, L₁ and L₂ elements can remain unchanged when changing the L₃ and C₉ components for other transmit powers.

When VS5V = 1 is selected, the VS_PA pin must be connected to an external capacitor only.

When VS5V = 0 is selected, the VS_PA pin must be connected to an external 3V supply.

If the user selects a 5V application instead of the 3V application, remove the 0Ω jumper at R1, and configure the ATA8510/15 for 5V application by enabling the VS_PA voltage regulator in the EEPROM configuration (eepTrxConf.sysConfig.VS5V).