11.3 Operations
The Clock Failure Detector (CFD) allows the user to monitor the low power crystal oscillator or external clock signal. CFD monitors XOSC clock and if it fails it will automatically switch to a safe clock. When operating on safe clock the device will switch back to XOSC clock after Power-On or External Reset, and continue monitoring XOSC clock for failures. The safe clock is derived from the 8MHz internal RC system clock. This allows to configure the safe clock in order to fulfill the operative conditions of the microcontroller.
Because the XOSC failure is monitored by the CFD circuit operating with the internal 128kHz oscillator, the current consumption of the 128kHz oscillator will be added into the total power consumption of the chip when CFD is enabled. CFD should be enabled only if the system clock (XOSC) frequency is above 256kHz.
Clock Failure Detection
To start the CFD operation, the user must write a one to the CFD fuse bit in the Extended Fuse Byte (EFB.CFD). After the start or restart of the XOSC, the CFD does not detect failure until the start-up time is elapsed. Once the XOSC Start-Up Time is elapsed, the XOSC clock is constantly monitored.
If the external clock is not provided, the device will automatically switch to calibrated RC oscillator output.
When the failure is detected, the failure status is asserted, i.e Failure Detection Interrupt Flag bit in the XOSC Failure Detection Control And Status Register (XFDCSR.XFDIF) is set. The Failure Detection interrupt flag is generated, when the Interrupt Enable bit in the XOSC Failure Detection Control And Status Register (XFDCSR.XFDIE) is set. The XFDCSR.XFDIF reflects the current XOSC clock activity.
The detection will be automatically disabled when chip goes to power save/down sleep mode and enabled by itself when chip enters back to active mode.Clock Switch
When a clock failure is detected, the XOSC clock is replaced by the safe clock in order to maintain an active clock. The safe clock source is the calibrated RC oscillator clock (CKSEL: 4’b0010). The clock source can be downscaled with a configurable prescaler to ensure that the clock frequency does not exceed the operating conditions selected by the application after switching. To use to original clock source, user must provide a reset. When using CFD and clock failure has occurred the system operates using 1MHz internal fallback clock. The system will try to resume to original clock source either via Power-On-Reset (POR) or via external RESET.