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AVR Microcontroller with Core Independent Peripherals and PicoPower technology ATmega324PB
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ATmega324PB
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29
JTAG Interface and On-chip Debug System
ATmega324PB
Introduction
Feature
1
Description
2
Configuration Summary
3
Ordering Information
4
Block Diagram
5
Pin Configurations
6
I/O Multiplexing
7
General Information
8
AVR CPU Core
9
AVR Memories
10
System Clock and Clock Options
11
CFD - Clock Failure Detection mechanism
12
PM - Power Management and Sleep Modes
13
SCRST - System Control and Reset
14
INT- Interrupts
15
External Interrupts
16
I/O-Ports
17
TC
0
- 8-bit Timer/Counter
0
with PWM
18
TC
1, 3, 4
- 16-bit Timer/Counter
1, 3, 4
with PWM
19
Timer/Counter 0, 1
, 3
, 4
Prescalers
20
TC
2
- 8-bit Timer/Counter
2
with PWM and Asynchronous Operation
21
OCM - Output Compare Modulator
22
SPI – Serial Peripheral Interface
23
USART - Universal Synchronous Asynchronous Receiver Transceiver
24
USARTSPI - USART in SPI Mode
25
TWI - 2-wire Serial Interface
26
AC - Analog Comparator
27
ADC - Analog to Digital Converter
28
PTC - Peripheral Touch Controller
29
JTAG Interface and On-chip Debug System
29.1
Features
29.2
Overview
29.3
TAP – Test Access Port
29.4
TAP Controller
29.5
Using the Boundary-scan Chain
29.6
Using the On-chip Debug System
29.7
On-chip Debug Specific JTAG Instructions
29.8
Using the JTAG Programming Capabilities
29.9
Bibliography
29.10
IEEE 1149.1 (JTAG) Boundary-scan
29.11
Data Registers
29.12
Boundry-scan Specific JTAG Instructions
29.13
Boundary-scan Chain
29.14
ATmega324PB
Boundary-scan Order
29.15
Boundary-scan Description Language Files
29.16
Register Description
30
BTLDR - Boot Loader Support – Read-While-Write Self-Programming
31
MEMPROG- Memory Programming
32
Electrical Characteristics
33
Typical Characteristics
34
Register Summary
35
Instruction Set Summary
36
Packaging Information
37
Errata
38
Datasheet Revision History
The Microchip Web Site
Customer Change Notification Service
Customer Support
Microchip Devices Code Protection Feature
Legal Notice
Trademarks
Quality Management System Certified by DNV
Worldwide Sales and Service
29 JTAG Interface and On-chip Debug System
