13.9.1 MCU Status
Register
To make use of the Reset
Flags to identify a reset condition, the user should read and then Reset the MCUSR as
early as possible in the program. If the register is cleared before another reset
occurs, the source of the reset can be found by examining the Reset Flags.When addressing I/O Registers as data space using LD
and ST instructions, the provided offset must be used. When using the I/O specific
commands IN and OUT, the offset is reduced by 0x20, resulting in an I/O address offset
within 0x00 - 0x3F.
| Name: | MCUSR |
| Offset: | 0x54 |
| Reset: | 0x00 |
| Property: | When addressing as I/O
Register: address offset is 0x34 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| | | | | JTRF | WDRF | BORF | EXTRF | PORF | |
| Access | | | | R/W | R/W | R/W | R/W | R/W | |
| Reset | | | | 0 | 0 | 0 | 0 | 0 | |
Bit 4 – JTRF JTAG Reset Flag
This bit is set if a reset is being caused by a logic one in the
JTAG Reset Register selected by the JTAG instruction AVR_RESET. This bit is reset by
a Power-on Reset, or by writing a logic zero to the flag.
Bit 3 – WDRF Watchdog System
Reset Flag
This bit is set if a
Watchdog System Reset occurs. The bit is reset by a Power-on Reset, or by writing a
'0' to it.
Bit 2 – BORF Brown-out Reset Flag
This bit is set if a
Brown-out Reset occurs. The bit is reset by a Power-on Reset, or by writing a '0' to
it.
Bit 1 – EXTRF External Reset Flag
This bit is set if
an External Reset occurs. The bit is reset by a Power-on Reset, or by writing a '0'
to it.
Bit 0 – PORF Power-on Reset Flag
This bit is set if a
Power-on Reset occurs. The bit is reset only by writing a '0' to it.
