14.3.37 ADC Early Interrupt Status Register High
| Name: | ADEISTATH |
| Offset: | 0xBFA |
Legend: HS = Hardware Settable bit; R = Readable bit
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| Access | |||||||||
| Reset |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| EISTAT[21:16] | |||||||||
| Access | HS/R | HS/R | HS/R | HS/R | HS/R | HS/R | |||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | |||
Bits 5:0 – EISTAT[21:16] Early Interrupt Status for Corresponding Analog Input bits
| Value | Description |
|---|---|
1 |
Early interrupt was generated. |
0 |
Early interrupt was not generated since the last ADCBUFx read. |