dsPIC33CDVL256MC506 Family Data Sheet

16.1.10 Velocity 1 Counter Hold Register

Name:	VEL1HLD
Offset:	0x15A


Bit	15	14	13	12	11	10	9	8
	VELHLDH[31:24]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0


Bit	7	6	5	4	3	2	1	0
	VELHLDH[23:16]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0

Bits 15:0 – VELHLDH[31:16] Hold Register for Reading and Writing Velocity Counter High Word Register (VEL1CNTH) bits

DS70005628B

The online versions of the documents are provided as a courtesy. Verify all content and data in the device’s PDF documentation found on the device product page.