4.3.1 FECCR – FEC Control Register

Name: FECCR
Offset: 0x0400
Reset: 0x00
Property: Read/Write

Bit 76543210 
 PBACNTE[4:0]SESD 
Access R/WR/WR/WR/WR/WR/WR/WR/W 
Reset 00000000 

Bit 7 – PBA Path B Active

Writing a logic one to this bit omits decryption of the first 2 FIFO bytes.

An opportunity to increase the likelihood to find a WCO/SOT in a noisy environment is to enable a second synchronization pattern (with 16-bit SOT length) on path B. To handle path A/B reception in decryption, this bit has to be set. This feature reduces the applicable payload length by 2 bytes.

ValueDescription
1 Second synchronization pattern on path B enabled (first 2 FIFO bytes are not used for decryption)
0 Second synchronization pattern on path B disabled

Bits 6:2 – CNTE[4:0] Count of Bytes to be Encrypted (valid values: 1-21)

Bit 1 – SE Start Encryption

Writing a logic one to this bit starts encryption of CNTE bytes in buffer FECTXDB[21] and fills FIFO. The bit is automatically cleared when encryption has finished.

Bit 0 – SD Start Decryption

Writing a logic one to this bit starts decryption of received data in FIFO and stores decrypted data to FECRXDB[21]. The bit is automatically cleared when encryption has finished.