38.5.1.6 System Clock

Table 38-15. System Clock Timing Characteristics
SymbolDescriptionMin.Typ. ✝Max.UnitConditions
fCLK_MAINMain clock frequency(1,2)——24MHz
fCYInstruction clock frequency—fCLK_MAIN—MHz
TCYInstruction period(3)41.61/fCY—ns

✝ Data in the “Typ.” column is at TA = 25°C and VDD = 3.0V unless otherwise specified. These parameters are not tested and are for design guidance only.

Note:
  1. The main clock frequency (CLK_MAIN) is configured by the Clock Select (CLKSEL) bit field, as described in the CLKCTRL - Clock Controller section.
  2. The main clock frequency (CLK_MAIN) must meet the voltage requirements defined in Standard Operating Conditions .
  3. The Instruction Cycle Period (TCY) is identical to the input oscillator time-base period. All specified values are based on characterization data for that particular oscillator type, under standard operating conditions with the device executing code. Exceeding these specified limits may result in incorrect code execution and/or higher than expected current consumption. All devices are tested to operate at ‘min’ values with an external clock applied to the EXTCLK pin. The ‘max’ cycle time limit is ‘DC’ (no clock) for all devices when using an external clock input.