5.2.2 MAC Frame Receive Data Block Footer

The following table depicts the breakdown of the 32-bit receive data block footer.

Table 5-3. Receive Data Block Footer Format
Bit	31	30	29	28	27	26	25	24
	EXST	HDRB	SYNC	RBA

Bit	23	22	21	20	19	18	17	16
	VS		DV	SV	SWO

Bit	15	14	13	12	11	10	9	8
	FD	EV	EBO

Bit	7	6	5	4	3	2	1	0
	RTSA	RTSP	TXC					P

Bit 31 - EXST: Extended Status - The LAN8650/1 sets this bit any time a status bit is set pending (and unmasked) within the Status 0 (OA_STATUS0) or Status 1 (OA_STATUS 1) registers.
Bit 30 - HDRB: Header Bad - Indication that the LAN8650/1 received a transaction header with an invalid parity.
Bit 29 - SYNC: Configuration Synchronized - This bit reflects the state of the Configuration Synchronization (SYNC) bit in the Configuration 0 (OA_CONFIG0) register. A zero indicates that the LAN8650/1 configuration may be unsynchronized with the SPI host. Following configuration, the SPI host shall set the SYNC bit within the OA_CONFIG0 register to enable the transfer of Ethernet frame data.
Bits 28:24 - RBA: Receive Blocks Available - This field reflects the minimum number of blocks of buffered frame data received from the network that is available for the MCU host to read from the LAN8650/1.
Bits 23:22 - VS: Vendor Specific - This field is reserved for future use. The LAN8650/1 will always set these bits to zero.
Bit 21 - DV: Data Valid - TheLAN8650/1 sets this bit to indicate to the SPI host that valid Ethernet frame data is being transferred within the data block payload.
Bit 20 - SV: Start Valid - This bit is set by the LAN8650/1 to indicate that the beginning of an Ethernet frame is contained within the data block payload. The beginning of the frame is located by the Start Word Offset (SWO) field. The SV bit is ignored if the Data Valid bit is ‘0’.
Bits 19:16 - SWO: Start Word Offset - This field indicates which 32-bit word of the data block payload contains the first word of a new Ethernet frame.
Bit 15 - FD: Frame Drop - This bit is set when the LAN8650/1 has detected an error in the received Ethernet frame indicating to the host MCU that the current frame received from SPI should be dropped. This bit is only valid when End Valid (EV) is set indicating the end of an Ethernet frame.
Bit 14 - EV: End Valid - This bit is set by the LAN8650/1 to indicate that the end of an Ethernet frame is contained within the data block payload. The end of the frame is located by the End Byte Offset (EBO) field. The EV bit is ignored if the Data Valid bit is ‘0’.
Bits 13:8 - EBO: End Byte Offset - This field indicated which byte of the data block payload contains the last byte of the end of an Ethernet frame. This field is ignored when Data Valid or End Valid bits are ‘0’.
Bit 7 - RTSA: Receive Timestamp Added - When set, this bit indicates that the LAN8650/1 has captured a frame ingress timestamp and added it to the beginning of the frame in the data block payload.
Bit 6 - RTSP: Receive Timestamp Parity - When an ingress frame timestamp has been captured and added to the beginning of a new frame in the data block payload as indicated by the Receive Timestamp Added (RTSA) bit being set, this bit contains the odd parity bit calculated over the timestamp.
Bits 5:1 - TXC: Transmit Credits - This field is used to indicate to the SPI host the number of transmit data blocks which may be sent to the LAN8650/1 without causing a buffer overflow.
Bit 0 - P: Parity - Parity bit over bits 31:1 of the receive data footer field. This field is set such that there is an odd total number of bits set within the footer.