5.1.5 Interrupts

The PIC16F, PIC18F and PIC32CM MCUs provide interrupt management systems that enable responsive and efficient handling of asynchronous events from peripherals and external sources. The PIC32CM uses the Arm Nested Vectored Interrupt (NVIC) that allows more complex interrupt nesting, priority management, and relocation. The table below provides a comparison of the features of the PIC16F, PIC18F, and PIC32CM MCUs.

Table 5-7. PIC16F, PIC18F, and PIC32CM Interrupt Features
FeaturePIC16F Interrupt Controller PIC18F Interrupt ControllerPIC32CM Nested Vectored Interrupt Controller (NVIC)
Interrupt ArchitectureSingle vector, software contextMultiple vectors, hardware contextNVIC (Nested Vectored Interrupt Controller)
Interrupt Prioritization No hardware priority (handled in software polling)Two-level hardware priority (high/low)Four programmable priority levels (M0+) Eight levels (M23 with Secure/Nonsecure split)
Non-Maskable InterruptN/AN/ASupported
Vector Table Single entry (ISR), software dispatchMultiple entries (ISR per source), hardware dispatchMultiple entries, hardware dispatch
Interrupt Sources Peripherals

External pins

Peripherals

External pins

Peripherals

External pins

Interrupt Flag HandlingSet/cleared in the peripheral and interrupt registersSet/cleared in the peripheral and interrupt registersSet/cleared in the peripheral and NVIC registers
Global Enable/DisableSupportedSupportedSupported
Response Time (minimum) 3 cycles3 cycles12-15 cycles
Priority ConfigurationSoftware pollingFully programmable per interruptFully programmable per interrupt
Scheduling SchemeSequential pollingHardware-based preemptionHardware-based preemption, and tail chaining
Security ContextN/AN/ASecure/Non-secure split (M23)
Nested InterruptsNot supportedSupportedFully supported (NVIC)
Wake up from SleepSupportedSupportedSupported
Interrupt LatencyHigher (software vectoring)Lower (hardware vectoring)Lowest (hardware vectoring, NVIC)