REN Connections

The REN signal on the generated component is connected to the write port block select input (A_BLK) for each LSRAM block according to the block depth within the component and synchronized with RCLK.

Table . REN Connections
DepthA_BLK[2]A_BLK[1]A_BLK[0]A_RENRead-Data when REN=0

RA_MSB < N

1

1

1

REN

Hold

RA_MSB = N

REN

1

decode( RADDR[N:N], D%2)

1

0

RA_MSB = N+1

REN

decode( RADDR[N+1:N+1], (D/ 2)%2)

decode (RADDR[N:N], D%2)

1

0

RA_MSB > N+1

REN & decode( RADDR[RA_MSB:N+2], D/4)

decode( RADDR[N+1:N+1], (D/ 2)%2)

decode (RADDR[N:N], D%2)

1

0

Note: Observe the different behaviors when REN is de-asserted on the top-level generated component:
  • If there is no depth cascading (RA_MSB < N), de-asserting REN holds the previously read-data.
  • If there is depth cascading (RA_MSB >= N), de-asserting REN generates zeros on the read-data.
The different behavior in these two scenarios occurs because the component's REN input is used to drive either the LSRAM block's A_REN input or the read-port block select input (A_BLK), depending on the cascading configuration.