RD Logic

The RD bits on the generated component are partitioned into slices based on the width of the data on the read port of each LSRAM block. Each bit of read-data from all blocks in a slice at every depth is OR’d together to generate a bit of RD. The RD bits are synchronized with RCLK according to the latency in the following table.

Table . RD Logic Latencies
ECC PipelineECCRD PipelineRD Latency

No

No

No

0

No

No

Yes

1

No

Yes

No

0

No

Yes

Yes

1

Yes

Yes

No

1

Yes

Yes

Yes

2