24.3.3 External Clock

External clocking is used by the synchronous slave modes of operation. The description in this section refers to Figure 24-2.

External clock input from the XCK pin is sampled by a synchronization register to minimize the chance of meta-stability. The output from the synchronization register must then pass through an edge detector before it can be used by the Transmitter and Receiver. This process introduces a two CPU clock period delay and therefore the maximum external XCK clock frequency is limited by the following equation:

f_{XCK} < \frac{f_{OSC}}{4}

The value of f_osc depends on the stability of the system clock source. It is therefore recommended to add some margin to avoid possible loss of data due to frequency variations.