24.3 Clock Generation

The clock generation logic generates the base clock for the Transmitter and Receiver. The USART supports four modes of clock operation: normal asynchronous, double speed asynchronous, Master synchronous and Slave Synchronous mode. The UMSEL bit in USART Control and Status Register C (UCSRC) selects between asynchronous and synchronous operation. Double speed (Asynchronous mode only) is controlled by the U2X found in the UCSRA Register. When using Synchronous mode (UMSEL = 1), the Data Direction Register for the XCK pin (DDR_XCK) controls whether the clock source is internal (Master mode) or external (Slave mode). The XCK pin is only active when using Synchronous mode.

Below is a block diagram of the clock generation logic.

Figure 24-2. Clock Generation Logic, Block Diagram

Signal description:

txclk: Transmitter clock (internal signal).
rxclk: Receiver base clock (internal signal).
xcki: Input from XCK pin (internal Signal). Used for synchronous slave operation.
xcko: Clock output to XCK pin (internal signal). Used for synchronous master operation.
fosc: XTAL pin frequency (System Clock).