5.13 Power Good

The Power Good (PG) pin is an open-drain output that requires an external pull-up resistor to a voltage not exceeding the input voltage in order to assert a logic-high level.

PG is asserted when the output voltage reaches 93% of its target regulation value. If the output voltage drops below 90% of the target, PG is deasserted after a typical delay of 50 μs, which serves as a deglitch timer to filter out short transients. PG is immediately deasserted if the EN pin falls below the enable threshold, or in the event of an undervoltage or thermal shutdown condition. The pull-up resistor should be selected to limit the PG pin current to less than 5 mA.