11.1.4 Recommended Operating Conditions

Table 11-4. Power Supply Inputs(8)
Power InputParameterConditionsMinMax Unit
VDDCPU(1)Cortex-A7 and cache memoriesfCPU_CLK ≤ 600 MHz1.031.21V
fCPU_CLK ≤ 800 MHz1.121.21V
fCPU_CLK ≤ 1 GHz(2) (SAMA7D65-V/4HB only)1.221.30V
VDDCORECore logic power supply1.031.21V
VDDIODDRSDRAM I/O lines power supply[LPDDR2 / LPDDR3]-SDRAM1.141.30V
DDR3-SDRAM1.4251.575V
DDR3L-SDRAM1.2831.45V
DDR2-SDRAM1.71.9V
VDDIN33(3)

VDDOUT25 regulator and OTP power supplies

Backup area power switch input

3.03.6V
VDDUTMII(3)USB device and host UTMI+ interface3.03.6V
VDDDPHY(4)MIPI D-PHY power supply2.42.6V
VDDANA(4)ADC, comparator, temperature sensor, PLLs, main crystal oscillator, main RC oscillator power supply2.42.6V
VDDIN25PLL LVDS power supply2.42.6V
VDDLVDS(5, 6)LVDS PHY and VDDLVDS I/O lines power supply1.73.6V
VDDIOP[0,1](5)Peripheral I/O lines1.73.6V
VDDGMAC[0,1]MAC Interface I/O lines1.73.6V
VDDQSPI[0,1](5)QSPIx I/O lines1.73.6V
VDDSDMMC[0,1,2](5)SDMMCx I/O lines1.73.6V
VBATBackup area power switch input1.73.6V
tR_VDDPower supply slope at power-upApplies to any of the power supply inputs listed above0.220mV/μs
tF_VDDPower supply slope at power-down-20-1(7)mV/μs
Note:
  1. For lifetime estimation as a function of operating voltage and junction temperature, contact a Microchip Sales Representative for further details.
  2. VDDCPU related alarms in SECUMOD_SR are always triggered when fCPU_CLK > 800 MHz
  3. VDDIN33 and VDDUTMII are powered from one single power source so that ΔV(VDDIN33,VDDUTMII) ≤ 50 mV.
  4. VDDANA, VDDIN25 and VDDDPHY must be connected to VDDOUT25.
  5. Supply range restrictions apply when using the digital peripheral timing characteristics. See I/O Characteristics.
  6. When the LVDS PHY is used, VDDLVDS must be connected to VDDOUT25.
  7. For VBAT, this value is 0 mV/μs.
  8. Refer to Microchip Recommended Power Management Solutions for a power supply schematic example with typical voltage regulator output values.
Table 11-5. Recommended Operating Conditions on Input Pins(1)
SymbolParameterConditionsMinMaxUnit
VINInput line voltage range on inputs(2)(3)-0.3VDD + 0.3V
IINDC current injection on inputs(4)(5)± 0.2mA
ITOT_INJTotal current injection per power rail or per ground rail(6)± 2mA
Note:
  1. In this table, VDD refers to the voltage of the associated power rail of the I/O line, as defined in the table Pin Description. Ex: for PA12, VDD refers to VDDSDMMC0.
  2. Input voltages VIN ≤ 0V or VIN ≥ VDD lead to negative or positive current injection on inputs.
  3. For A/D converter analog inputs (PB28, PB29, PC3, PC4, PC5, PC6, PC7, PC10, PC11, PC12, PC13, PC14, PC15, PC16, PC22), input voltages VIN ≥ min(VDDANA, VADVREFP) lead to saturated A/D conversion to 0xFFF.
  4. Current injection on A/D converter analog inputs (PB28, PB29, PC3, PC4, PC5, PC6, PC7, PC10, PC11, PC12, PC13, PC14, PC15, PC16, PC22) may degrade the analog performance of the corresponding channel, or the analog performance of other analog channels.
  5. High frequency current injection must be limited to avoid propagating high frequency signals to internal sensitive analog circuits (oscillators, regulators, etc.). One common use case of high frequency current injection occurs when a digital input pin suffers overshoots and/or undershoots from a poorly adapted transmission line (PCB trace with signal reflections, for example). These cases should be cured by appropriate source series resistor termination. Special attention must be paid to high-speed interfaces (Gigabit Ethernet MAC I/F, SD Card or e.MMC I/F, QSPI I/F, etc.).
  6. Corresponds to the sum of the positive currents into one power rail and, respectively, to the sum of the negative currents into one ground rail, as defined in the table Pin Description.
Table 11-6. Recommended Operating Conditions on Internal Clocks
SymbolParameterConditionsMinMaxUnit
fCPU_CLKProcessor clock (CPU_CLK) frequencyVDDCPU ≥ 1.22V (SAMA7D65-V/4HB only)1000MHz
VDDCPU ≥ 1.12V800MHz
VDDCPU ≥ 1.03V600MHz
fMCK0Main system bus clock (MCK0) frequency200MHz
fMCK1Main system bus clock (MCK1) frequency200MHz
fMCK2Main system bus clock (MCK2) frequency133MHz
fMCK3Main system bus clock (MCK3) frequency266MHz
fMCK4Main system bus clock (MCK4) frequency400MHz
fMCK5Main system bus clock (MCK5) frequency200MHz
fMCK6Main system bus clock (MCK6) frequency200MHz
fMCK7Main system bus clock (MCK7) frequency100MHz
fMCK8Main system bus clock (MCK8) frequency100MHz
fMCK9Main system bus clock (MCK9) frequency100MHz
Table 11-7. Recommended Operating Conditions on SDRAM Interface
SymbolParameterConditionsMinMaxUnit
fDDR_CLKSDRAM clock frequency[LPDDR2 / LPDDR3]-SDRAM100533MHz
[DDR3 / DDR3L]-SDRAM100533MHz
DDR2-SDRAM125533MHz
Table 11-8. Recommended Thermal Operating Conditions(1)
SymbolParameterConditionsMinMaxUnit
TJJunction temperature rangeOrdering Code SAMA7D65-V/4HB-40105°C
Note:
  1. For lifetime estimation as a function of operating voltage and junction temperature, refer to the application note "SAMA7 Product Lifetime Estimation" (AN4532) on www.microchip.com.
Table 11-9. BGA343 Package Thermal Characteristics(1)(2)
SymbolParameterTypUnit
RJAJunction-to-ambient thermal resistance25°C/W
RJBJunction-to-board thermal resistance18°C/W
RJCJunction-to-case thermal resistance8°C/W
ΨJTJunction-to-package-top characterization parameter0.3°C/W
Note:
  1. According to the JEDEC JESD51-2 standard, with 2s2p board and 0 m/s air flow.
  2. The package characteristics in the above table are provided according to the JEDEC JESD51-2 standard with the 2s2p board and 0 m/s air flow. These values are not directly applicable to the final application. As per JEDEC standards, these parameters represent the device mounted on a specific PCB under controlled conditions. In real-world applications, the PCB design and construction, airflow, and other factors may significantly impact thermal characteristics.