1.8.2 Pin Description

The device features several PIO controllers that multiplex the I/O lines of the peripheral set. The following Pin Description table defines how the I/O lines are multiplexed on the different PIO controllers. The "Reset State" column shows whether the PIO line resets in I/O mode or in Peripheral mode. If I/O is shown, the PIO line resets with the characteristics (input, output, pull-up or pull-down) indicated in this same column, so that the device is configured in a known state as soon as the reset is released. As a result, PIO_CFGR.FUNC resets to ‘0’. If a signal name is shown in the “Reset State” column, the PIO line is assigned to this function and PIO_CFGR.FUNC is not set to ‘0’. That is the case for pins controlling memories, in particular address lines, which require the pin to be driven as soon as the reset is released.

Table 1-1. Pin Description⁽¹⁾⁽²⁾
343-pin TFBGA	Power Rail	I/O Type⁽³⁾	Primary		Alternate		PIO Peripheral				Reset State
343-pin TFBGA	Power Rail	I/O Type⁽³⁾	Signal	Dir	Signal	Dir	Func	Signal	Dir	I/O Set	Signal, Dir, PU, PD, HiZ, ST⁽⁴⁾
U18	VDDSDMMC0	HSIO	PA0	I/O	–	–	A	SDMMC0_CK	O	1	PIO, I, PU, ST
							B	FLEXCOM3_IO0	I/O	1
							C	NWE/NWR0/NANDWE	O	1
V17	VDDSDMMC0	HSIO	PA1	I/O	–	–	A	SDMMC0_CMD	I/O	1	PIO, I, PU, ST
							B	FLEXCOM3_IO1	I/O	1
							C	A21/NANDALE	O	1,2
R14	VDDSDMMC0	HSIO	PA2	I/O	–	–	A	SDMMC0_RSTN	O	1	PIO, I, PU, ST
							B	FLEXCOM3_IO2	I/O	1
							C	A22/NANDCLE	O	1,2
T18	VDDSDMMC0	HSIO	PA3	I/O	–	–	A	SDMMC0_DAT0	I/O	1	PIO, I, PU, ST
							B	FLEXCOM3_IO3	I/O	1
							C	D0	I/O	1
P16	VDDSDMMC0	HSIO	PA4	I/O	–	–	A	SDMMC0_DAT1	I/O	1	PIO, I, PU, ST
							B	FLEXCOM3_IO4	O	1
							C	D1	I/O	1
V16	VDDSDMMC0	HSIO	PA5	I/O	–	–	A	SDMMC0_DAT4	I/O	1	PIO, I, PU, ST
							B	FLEXCOM2_IO0	I/O	3
							C	D4	I/O	1
							F	TCLK4	I	3
T14	VDDSDMMC0	HSIO	PA6	I/O	–	–	A	SDMMC0_DAT5	I/O	1	PIO, I, PU, ST
							B	FLEXCOM2_IO1	I/O	3
							C	D5	I/O	1
							F	TIOB4	I/O	3
P15	VDDSDMMC0	HSIO	PA7	I/O	–	–	A	SDMMC0_DAT6	I/O	1	PIO, I, PU, ST
							B	FLEXCOM2_IO2	I/O	3
							C	D6	I/O	1
							F	TIOA4	I/O	3
R13	VDDSDMMC0	HSIO	PA8	I/O	–	–	A	SDMMC0_DAT7	I/O	1	PIO, I, PU, ST
							B	FLEXCOM2_IO3	I/O	3
							C	D7	I/O	1
							F	TIOA5	I/O	3
U14	VDDSDMMC0	HSIO	PA9	I/O	–	–	A	SDMMC0_DAT2	I/O	1	PIO, I, PU, ST
							B	FLEXCOM0_IO2	I/O	1
							C	D2	I/O	1
							F	TIOB5	I/O	3
R12	VDDSDMMC0	HSIO	PA10	I/O	–	–	A	SDMMC0_DAT3	I/O	1	PIO, I, PU, ST
							B	FLEXCOM0_IO3	I/O	1
							C	D3	I/O	1
							F	TCLK5	I	3
P12	VDDSDMMC0	HSIO	PA11	I/O	–	–	A	SDMMC0_DS	I	1	PIO, I, PU, ST
							B	FLEXCOM0_IO4	O	1
							C	NANDRDY	I	1,2
							F	TIOB3	I/O	3
W15	VDDSDMMC0	HSIO	PA12	I/O	–	–	B	FLEXCOM0_IO0	I/O	1	PIO, I, PU, ST
							C	NRD/NANDOE	O	1,2
							D	PCK0	O	1
							E	EXT_IRQ0	I	1
							F	TIOA3	I/O	3
P11	VDDSDMMC0	HSIO	PA13	I/O	–	–	B	FLEXCOM0_IO1	I/O	1	PIO, I, PU, ST
							C	NCS0/NANDCS0	O	1,2
							D	PCK1	O	1
							F	TCLK3	I	3
V14	VDDIOP0	GPIO	PA14	I/O	–	–	A	FLEXCOM4_IO4	O	1	PIO, I, PU, ST
							B	SDMMC0_WP	I	1
							C	FLEXCOM3_IO0	I/O	4
N11	VDDIOP0	GPIO	PA15	I/O	–	–	A	FLEXCOM4_IO3	I/O	1	PIO, I, PU, ST
							B	SDMMC0_1V8SEL	O	1
							C	FLEXCOM3_IO1	I/O	4
V15	VDDIOP0	GPIO	PA16	I/O	–	–	A	FLEXCOM4_IO2	I/O	1	PIO, I, PU, ST
							B	SDMMC0_CD	I	1
							D	PCK2	O	1
							E	EXT_IRQ1	I	1
R9	VDDIOP0	GPIO	PA17	I/O	–	–	A	FLEXCOM4_IO1	I/O	1	PIO, I, PU, ST
W16	VDDIOP0	GPIO	PA18	I/O	–	–	A	FLEXCOM4_IO0	I/O	1	PIO, I, PU, ST
W18	VDDIOP0	GPIO	PA19	I/O	–	–	A	TK0	I/O	1	PIO, I, PU, ST
							C	FLEXCOM4_IO5	O	1
							D	PWML0	O	3
R10	VDDIOP0	GPIO	PA20	I/O	–	–	A	TD0	O	1	PIO, I, PU, ST
							B	FLEXCOM3_IO4	O	2
							C	FLEXCOM4_IO6	O	1
							D	PWMH0	O	3
W19	VDDIOP0	GPIO	PA21	I/O	–	–	A	TF0	I/O	1	PIO, I, PU, ST
							B	FLEXCOM3_IO3	I/O	2
							D	PWML1	O	3
P10	VDDIOP0	GPIO	PA22	I/O	–	–	A	RD0	I	1	PIO, I, PU, ST
							B	FLEXCOM3_IO2	I/O	2
							C	PDMC0_DS1	I	1
							D	PWMH1	O	3
AA20	VDDIOP0	GPIO	PA23	I/O	–	–	A	RK0	I/O	1	PIO, I, PU, ST
							B	FLEXCOM3_IO1	I/O	2
							C	PDMC0_CLK	O	1
							D	PWML2	O	3
P9	VDDIOP0	GPIO	PA24	I/O	–	–	A	RF0	I/O	1	PIO, I, PU, ST
							B	FLEXCOM3_IO0	I/O	2
							C	PDMC0_DS0	I	1
							D	PWMH2	O	3
B21	VDDGMAC0	GPIO	PA25	I/O	–	–	A	G0_TXCTL/G0_TXEN	O	1,2	PIO, I, PU, ST
B21	VDDGMAC0	GPIO	PA25	I/O	–	–	B	FLEXCOM6_IO2	I/O	1	PIO, I, PU, ST
K14	VDDGMAC0	GPIO	PA26	I/O	–	–	A	G0_TX0	O	1,2	PIO, I, PU, ST
K14	VDDGMAC0	GPIO	PA26	I/O	–	–	B	FLEXCOM6_IO3	I/O	1	PIO, I, PU, ST
C21	VDDGMAC0	GPIO	PA27	I/O	–	–	A	G0_TX1	O	1,2	PIO, I, PU, ST
C21	VDDGMAC0	GPIO	PA27	I/O	–	–	B	FLEXCOM6_IO4	O	1	PIO, I, PU, ST
L13	VDDGMAC0	GPIO	PA28	I/O	–	–	A	G0_RXCTL/G0_CRSDV	I	1,2	PIO, I, PU, ST
L13	VDDGMAC0	GPIO	PA28	I/O	–	–	B	FLEXCOM6_IO0	I/O	1	PIO, I, PU, ST
D21	VDDGMAC0	GPIO	PA29	I/O	–	–	A	G0_RX0	I	1,2	PIO, I, PU, ST
D21	VDDGMAC0	GPIO	PA29	I/O	–	–	B	FLEXCOM6_IO1	I/O	1	PIO, I, PU, ST
K15	VDDGMAC0	GPIO	PA30	I/O	–	–	A	G0_RX1	I	1,2	PIO, I, PU, ST
K15	VDDGMAC0	GPIO	PA30	I/O	–	–	B	FLEXCOM8_IO0	I/O	1	PIO, I, PU, ST
F21	VDDGMAC0	GPIO	PA31	I/O	–	–	A	G0_MDC	O	1,2	PIO, I, PU, ST
F21	VDDGMAC0	GPIO	PA31	I/O	–	–	B	FLEXCOM8_IO1	I/O	1	PIO, I, PU, ST
M10	VDDGMAC0	GPIO	PB0	I/O	–	–	A	G0_MDIO	I/O	1,2	PIO, I, PU, ST
M10	VDDGMAC0	GPIO	PB0	I/O	–	–	B	FLEXCOM8_IO3	I/O	1	PIO, I, PU, ST
G21	VDDGMAC0	GPIO	PB1	I/O	–	–	A	G0_REFCK/G0_TXCK	I/O	2,1	PIO, I, PU, ST
G21	VDDGMAC0	GPIO	PB1	I/O	–	–	B	FLEXCOM8_IO2	I/O	1	PIO, I, PU, ST
J14	VDDGMAC0	GPIO	PB2	I/O	–	–	A	G0_RX2	I	1	PIO, I, PU, ST
							B	FLEXCOM8_IO4	O	1
							C	G0_RXER	I	2
							D	RK0	I/O	2
J21	VDDGMAC0	GPIO	PB3	I/O	–	–	A	G0_RXCK	I	1	PIO, I, PU, ST
							B	FLEXCOM10_IO2	I/O	2
							D	TK0	I/O	2
J15	VDDGMAC0	GPIO	PB4	I/O	–	–	A	G0_TX2	O	1	PIO, I, PU, ST
							B	FLEXCOM10_IO3	I/O	2
							D	TF0	I/O	2
J20	VDDGMAC0	GPIO	PB5	I/O	–	–	A	G0_TX3	O	1	PIO, I, PU, ST
							B	FLEXCOM10_IO4	O	2
							D	TD0	O	2
K13	VDDGMAC0	GPIO	PB6	I/O	–	–	A	G0_RX3	I	1	PIO, I, PU, ST
							B	FLEXCOM10_IO0	I/O	2
							D	RD0	I	2
C20	VDDGMAC0	GPIO	PB7	I/O	–	–	A	G0_TSUCOMP	O	1,2	PIO, I, PU, ST
							B	FLEXCOM10_IO1	I/O	2
							C	ADTRG	I	1
							D	RF0	I/O	2
T19	VDDQSPI0	HSIO	PB8	I/O	–	–	A	QSPI0_IO3	I/O	1	PIO, I, PU, ST
							B	PCK3	O	1
							D	FLEXCOM2_IO1	I/O	2
R18	VDDQSPI0	HSIO	PB9	I/O	–	–	A	QSPI0_IO2	I/O	1	PIO, I, PU, ST
							D	FLEXCOM2_IO0	I/O	2
							E	PWMEXTRG0	I	1
P17	VDDQSPI0	HSIO	PB10	I/O	–	–	A	QSPI0_IO1	I/O	1	PIO, I, PU, ST
							D	FLEXCOM2_IO4	O	2
							E	PWMEXTRG1	I	1
R19	VDDQSPI0	HSIO	PB11	I/O	–	–	A	QSPI0_IO0	I/O	1	PIO, I, PU, ST
							D	FLEXCOM2_IO5	O	2
							E	PWML3	O	1
							F	TIOB3	I/O	2
P18	VDDQSPI0	HSIO	PB12	I/O	–	–	A	QSPI0_CS	O	1	PIO, I, PU, ST
							D	FLEXCOM2_IO3	I/O	2
							E	PWMFI1	I	1
							F	TIOA3	I/O	2
N14	VDDQSPI0	HSIO	PB13	I/O	–	–	A	QSPI0_SCK	O	1	PIO, I, PU, ST
							D	FLEXCOM2_IO2	I/O	2
							E	PWMFI0	I	1
							F	TCLK3	I	2
N15	VDDQSPI0	HSIO	PB14	I/O	–	–	A	QSPI0_SCKN	O	1	PIO, I, PU, ST
							B	QSPI1_SCK	O	1
							C	I2SMCC0_CK	I/O	3
							D	FLEXCOM10_IO5	O	1
							E	PWMH3	O	1
							G	FLEXCOM2_IO1	I/O	4
M15	VDDQSPI0	HSIO	PB15	I/O	–	–	A	QSPI0_IO4	I/O	1	PIO, I, PU, ST
							B	QSPI1_IO0	I/O	1
							C	I2SMCC0_WS	I/O	3
							D	FLEXCOM10_IO6	O	1
							E	PWML0	O	1
							F	TCLK4	I	2
							G	FLEXCOM2_IO0	I/O	4
N20	VDDQSPI0	HSIO	PB16	I/O	–	–	A	QSPI0_IO5	I/O	1	PIO, I, PU, ST
							B	QSPI1_IO1	I/O	1
							C	I2SMCC0_DIN0	I	3
							D	FLEXCOM10_IO4	O	1
							E	PWMH0	O	1
							F	TIOB4	I/O	2
M14	VDDQSPI0	HSIO	PB17	I/O	–	–	A	QSPI0_IO6	I/O	1	PIO, I, PU, ST
							B	QSPI1_IO2	I/O	1
							C	I2SMCC0_DOUT0	O	3
							D	FLEXCOM10_IO3	I/O	1
							E	PWML1	O	1
							F	TIOA4	I/O	2
N21	VDDQSPI0	HSIO	PB18	I/O	–	–	A	QSPI0_IO7	I/O	1	PIO, I, PU, ST
							B	QSPI1_IO3	I/O	1
							C	I2SMCC0_MCK	O	3
							D	FLEXCOM10_IO2	I/O	1
							E	PWMH1	O	1
							F	TIOA5	I/O	2
L14	VDDQSPI0	HSIO	PB19	I/O	–	–	A	QSPI0_DQS	I	1	PIO, I, PU, ST
							B	EXT_IRQ1	I	2
							C	PCK4	O	1
							D	FLEXCOM10_IO1	I/O	1
							E	PWML2	O	1
							F	TIOB5	I/O	2
M12	VDDQSPI0	HSIO	PB20	I/O	–	–	A	QSPI0_INT	I	1	PIO, I, PU, ST
							B	QSPI1_CS	O	1
							D	FLEXCOM10_IO0	I/O	1
							E	PWMH2	O	1
							F	TCLK5	I	2
D15	VDDSDMMC1	HSIO	PB21	I/O	–	–	A	SDMMC1_RSTN	O	1	PIO, I, PU, ST
							B	FLEXCOM6_IO4	O	2
							C	TIOB2	I/O	2
							D	ADTRG	I	2
							E	EXT_IRQ0	I	2
C14	VDDSDMMC1	HSIO	PB22	I/O	–	–	A	SDMMC1_CMD	I/O	1	PIO, I, PU, ST
							B	FLEXCOM6_IO3	I/O	2
							C	TCLK2	I	2
D14	VDDSDMMC1	HSIO	PB23	I/O	–	–	A	SDMMC1_CK	O	1	PIO, I, PU, ST
							B	FLEXCOM6_IO2	I/O	2
							C	TIOA2	I/O	2
B15	VDDSDMMC1	HSIO	PB24	I/O	–	–	A	SDMMC1_DAT0	I/O	1	PIO, I, PU, ST
B15	VDDSDMMC1	HSIO	PB24	I/O	–	–	B	FLEXCOM6_IO0	I/O	2	PIO, I, PU, ST
A13	VDDSDMMC1	HSIO	PB25	I/O	–	–	A	SDMMC1_DAT1	I/O	1	PIO, I, PU, ST
							B	FLEXCOM6_IO1	I/O	2
							C	TIOB2	I/O	1
A15	VDDSDMMC1	HSIO	PB26	I/O	–	–	A	SDMMC1_DAT2	I/O	1	PIO, I, PU, ST
							B	FLEXCOM8_IO0	I/O	3
							C	TCLK2	I	1
C11	VDDSDMMC1	HSIO	PB27	I/O	–	–	A	SDMMC1_DAT3	I/O	1	PIO, I, PU, ST
							B	FLEXCOM8_IO1	I/O	3
							C	TIOA2	I/O	1
C3	VDDIN33	GPIO	PB28	I/O	AD12	I	A	SDMMC1_WP	I	1	PIO, I, PU, ST
							C	FLEXCOM1_IO0	I/O	3
							E	D15	I/O	1,2
G4	VDDIN33	GPIO	PB29	I/O	AD13	I	A	SDMMC1_CD	I	1	PIO, I, PU, ST
							B	I2SMCC0_MCK	O	1
							C	FLEXCOM1_IO1	I/O	3
							E	D14	I/O	1,2
A2	VDDIN33	GPIO	PB30	I/O	AD14	I	A	SDMMC1_1V8SEL	O	1	PIO, I, PU, ST
							B	I2SMCC1_MCK	O	1
							C	FLEXCOM1_IO2	I/O	3
							D	TIOA1	I/O	1
							E	NCS1/NANDCS1	O	1,2
C5	VDDIN33	GPIO	PB31	I/O	HHSA_CC1	I/O	A	PCK7	O	2	PIO, I, PU, ST
							B	I2SMCC1_DIN1	I	1
							C	FLEXCOM1_IO3	I/O	3
							D	TCLK1	I	1
							E	NWE/NWR0/NANDWE	O	2
J8	VDDIN33	GPIO	PC0	I/O	HHSA_CC2	I/O	A	PCK6	O	2	PIO, I, PU, ST
							B	I2SMCC1_DIN2	I	1
							C	FLEXCOM9_IO4	O	2
							D	TIOB1	I/O	1
							E	NWR1/NBS1	O	1,2
C8	VDDIN33	GPIO	PC1	I/O	HHSB_CC1	I/O	A	PCK5	O	1	PIO, I, PU, ST
							C	FLEXCOM9_IO2	I/O	2
							E	SMCK	O	1,2
D7	VDDIN33	GPIO	PC2	I/O	HHSB_CC2	I/O	A	EXT_IRQ0	I	3	PIO, I, PU, ST
							C	FLEXCOM9_IO3	I/O	2
							E	A11	O	1,2
G8	VDDIN33	GPIO	PC3	I/O	AD0	I	A	SPDIF_RX	I	2	PIO, I, PU, ST
							C	FLEXCOM9_IO0	I/O	2
							D	FLEXCOM0_IO4	O	2
							E	A10	O	1,2
C2	VDDIN33	GPIO	PC4	I/O	AD1	I	A	SPDIF_TX	O	2	PIO, I, PU, ST
							C	FLEXCOM9_IO1	I/O	2
							D	FLEXCOM0_IO3	I/O	2
							E	D0	I/O	2
G3	VDDIN33	GPIO	PC5	I/O	AD2	I	A	I3CC_SDASPUE	O	1	PIO, I, PU, ST
							B	I2SMCC1_DIN3	I	1
							D	FLEXCOM0_IO2	I/O	2
							E	D1	I/O	2
H6	VDDIN33	GPIO	PC6	I/O	AD3	I	A	I3CC_SCL	I/O	1	PIO, I, PU, ST
							D	FLEXCOM0_IO1	I/O	2
							E	D4	I/O	2
B1	VDDIN33	GPIO	PC7	I/O	AD4	I/O	A	I3CC_SDA	I/O	1	PIO, I, PU, ST
							D	FLEXCOM0_IO0	I/O	2
							E	D5	I/O	2
E6	VDDIN33	GPIO	PC8	I/O	ACC_INP1	I	A	I2SMCC0_DIN1	I	1	PIO, I, PU, ST
							B	PDMC0_DS1	I	2
							C	I2SMCC1_DOUT1	O	1
							D	FLEXCOM9_IO0	I/O	1
							E	D6	I/O	2
D6	VDDIN33	GPIO	PC9	I/O	ACC_INN1	I	A	I2SMCC0_DIN2	I	1	PIO, I, PU, ST
							B	PDMC0_CLK	O	2
							C	I2SMCC1_DOUT2	O	1
							D	FLEXCOM9_IO1	I/O	1
							E	D7	I/O	2
H7	VDDIN33	GPIO	PC10	I/O	AD5	I/O	A	I2SMCC0_DIN3	I	1	PIO, I, PU, ST
							B	PDMC0_DS0	I	2
							C	I2SMCC1_DOUT3	O	1
							D	FLEXCOM9_IO2	I/O	1
							E	D2	I/O	2
C1	VDDIN33	GPIO	PC11	I/O	AD6	I	A	I2SMCC0_DOUT1	O	1	PIO, I, PU, ST
							B	PDMC1_DS0	I	1
							D	FLEXCOM9_IO3	I/O	1
							E	D3	I/O	2
H5	VDDIN33	GPIO	PC12	I/O	AD7	I	A	I2SMCC0_DOUT2	O	1	PIO, I, PU, ST
							B	PDMC1_CLK	O	1
							D	FLEXCOM9_IO4	O	1
							E	A9	O	1,2
D1	VDDIN33	GPIO	PC13	I/O	AD8	I	A	I2SMCC0_DOUT3	O	1	PIO, I, PD, ST
							B	PDMC1_DS1	I	1
							E	A8	O	1,2
J7	VDDIN33	GPIO	PC14	I/O	AD9	I	A	I2SMCC1_DIN0	I	1	PIO, I, PD, ST
							B	SPDIF_RX	I	3
							C	FLEXCOM1_IO0	I/O	2
							E	A7	O	1,2
F3	VDDIN33	GPIO	PC15	I/O	AD10	I	A	I2SMCC1_WS	I/O	1	PIO, I, PD, ST
							B	PDMC1_DS1	I	2
							C	FLEXCOM1_IO1	I/O	2
							E	A6	O	1,2
H4	VDDIN33	GPIO	PC16	I/O	AD11	I	A	I2SMCC1_CK	I/O	1	PIO, I, PD, ST
							B	PDMC1_CLK	O	2
							C	FLEXCOM1_IO2	I/O	2
							D	TIOA1	I/O	2
							E	A5	O	1,2
D4	VDDIN33	GPIO	PC17	I/O	ACC_INP0	I	A	I2SMCC1_DOUT0	O	1	PIO, I, PU, ST
							B	PDMC1_DS0	I	2
							C	FLEXCOM1_IO3	I/O	2
							D	TCLK1	I	2
							E	A4	O	1,2
F7	VDDIN33	GPIO	PC18	I/O	ACC_INN2	I	A	I2SMCC0_DIN0	I	1	PIO, I, PU, ST
							B	SPDIF_TX	O	3
							C	FLEXCOM1_IO4	O	2
							D	TIOB1	I/O	2
							E	A3	O	1,2
D5	VDDIN33	GPIO	PC19	I/O	ACC_INP2	I	A	I2SMCC0_WS	I/O	1	PIO, I, PU, ST
							B	PCK6	O	1
							E	A2	O	1,2
C6	VDDIN33	GPIO	PC20	I/O	ACC_INN3	–	A	I2SMCC0_DOUT0	O	1	PIO, I, PU, ST
C6	VDDIN33	GPIO	PC20	I/O	ACC_INN3	–	E	A1	O	1,2	PIO, I, PU, ST
F8	VDDIN33	GPIO	PC21	I/O	ACC_INP3	–	A	I2SMCC0_CK	I/O	1	PIO, I, PU, ST
							B	PCK7	O	1
							E	A0/NBS0	O	1,2
F4	VDDIN33	GPIO	PC22	I/O	AD15	–	A	NTRST	I	1	NTRST, PU, ST
F4	VDDIN33	GPIO	PC22	I/O	AD15	–	E	NWAIT	I	1,2	NTRST, PU, ST
A3	VDDIN33	GPIO	PC23	I/O	–	–	A	TCK_SWCLK	I	1	TCK_SWCLK, ST
F5	VDDIN33	GPIO	PC24	I/O	–	–	A	TMS_SWDIO	I/O	1	TMS_SWDIO, PU, ST
B3	VDDIN33	GPIO	PC25	I/O	–	–	A	TDI	I	1	TDI, PU, ST
G6	VDDIN33	GPIO	PC26	I/O	–	–	A	TDO	O	1	TDO, ST
G6	VDDIN33	GPIO	PC26	I/O	–	–	E	A12	O	1,2	TDO, ST
C15	VDDSDMMC2	HSIO	PC27	I/O	–	–	A	SDMMC2_CMD	I/O	1	PIO, I, PU, ST
							B	FLEXCOM8_IO0	I/O	2
							D	TD1	O	2
							E	D8	I/O	1,2
D16	VDDSDMMC2	HSIO	PC28	I/O	–	–	A	SDMMC2_CK	O	1	PIO, I, PU, ST
							B	FLEXCOM8_IO1	I/O	2
							D	TF1	I/O	2
							E	D9	I/O	1,2
B16	VDDSDMMC2	HSIO	PC29	I/O	–	–	A	SDMMC2_DAT0	I/O	1	PIO, I, PU, ST
							B	FLEXCOM8_IO2	I/O	2
							D	TK1	I/O	2
							E	D10	I/O	1,2
							F	TCLK0	I	1
D17	VDDSDMMC2	HSIO	PC30	I/O	–	–	A	SDMMC2_DAT1	I/O	1	PIO, I, PU, ST
							B	FLEXCOM8_IO3	I/O	2
							D	RD1	I	2
							E	D11	I/O	1,2
							F	TIOA0	I/O	1
A16	VDDSDMMC2	HSIO	PC31	I/O	–	–	A	SDMMC2_DAT2	I/O	1	PIO, I, PU, ST
							B	FLEXCOM8_IO4	O	2
							C	PCK0	O	2
							D	RK1	I/O	2
							E	D12	I/O	1,2
							F	TIOB0	I/O	1
C16	VDDSDMMC2	HSIO	PD0	I/O	–	–	A	SDMMC2_DAT3	I/O	1	PIO, I, PU, ST
							C	PCK1	O	2
							D	RF1	I/O	2
							E	D13	I/O	1,2
A18	VDDIOP1	GPIO	PD1	I/O	–	–	A	SDMMC2_WP	I	1	PIO, I, PU, ST
							B	FLEXCOM1_IO5	O	1
							C	LCDC_HSYNC	O	2
							D	FLEXCOM3_IO0	I/O	3
G13	VDDIOP1	GPIO	PD2	I/O	–	–	A	SDMMC2_CD	I	1	PIO, I, PU, ST
							B	FLEXCOM1_IO6	O	1
							C	LCDC_VSYNC	O	2
							D	FLEXCOM3_IO1	I/O	3
B18	VDDIOP1	GPIO	PD3	I/O	–	–	A	SDMMC2_1V8SEL	O	1	PIO, I, PU, ST
							B	FLEXCOM1_IO4	O	1
							C	TIOA0	I/O	2
							D	FLEXCOM3_IO2	I/O	3
							E	EXT_IRQ1	I	3
G12	VDDIOP1	GPIO	PD4	I/O	–	–	A	LCDC_HSYNC	O	1	PIO, I, PU, ST
							B	FLEXCOM1_IO2	I/O	1
							C	TIOB0	I/O	2
							D	FLEXCOM7_IO1	I/O	3
A19	VDDIOP1	GPIO	PD5	I/O	–	–	A	LCDC_VSYNC	O	1	PIO, I, PU, ST
							B	FLEXCOM1_IO3	I/O	1
							C	TCLK0	I	2
							D	FLEXCOM7_IO0	I/O	3
G10	VDDIOP1	GPIO	PD6	I/O	–	–	A	LCDC_PWM	O	1,2	PIO, I, PU, ST
							B	FLEXCOM1_IO1	I/O	1
							D	FLEXCOM7_IO2	I/O	3
A20	VDDIOP1	GPIO	PD7	I/O	–	–	A	LCDC_DISP	O	1,2	PIO, I, PU, ST
							B	FLEXCOM1_IO0	I/O	1
							D	FLEXCOM7_IO3	I/O	3
G14	VDDIOP1	GPIO	PD8	I/O	–	–	A	CANTX0	O	1	PIO, I, PU, ST
G14	VDDIOP1	GPIO	PD8	I/O	–	–	B	FLEXCOM7_IO0	I/O	1	PIO, I, PU, ST
F14	VDDIOP1	GPIO	PD9	I/O	–	–	A	CANRX0	I	1	PIO, I, PU, ST
F14	VDDIOP1	GPIO	PD9	I/O	–	–	B	FLEXCOM7_IO1	I/O	1	PIO, I, PU, ST
G16	VDDIOP1	GPIO	PD10	I/O	–	–	A	CANTX1	O	1	PIO, I, PU, ST
							B	FLEXCOM7_IO2	I/O	1
							C	TIOA1	I/O	3
H11	VDDIOP1	GPIO	PD11	I/O	–	–	A	CANRX1	I	1	PIO, I, PU, ST
							B	FLEXCOM7_IO3	I/O	1
							C	TCLK1	I	3
D18	VDDIOP1	GPIO	PD12	I/O	–	–	A	CANTX2	O	1	PIO, I, PU, ST
							B	FLEXCOM7_IO4	O	1
							C	TIOB1	I/O	3
							D	PCK2	O	2
							E	FLEXCOM3_IO3	I/O	3
J11	VDDIOP1	GPIO	PD13	I/O	–	–	A	CANRX2	I	1	PIO, I, PU, ST
							B	FLEXCOM5_IO4	O	1
							C	TIOA2	I/O	3
							D	PCK3	O	2
C18	VDDIOP1	GPIO	PD14	I/O	–	–	A	CANTX3	O	1	PIO, I, PU, ST
							B	FLEXCOM5_IO2	I/O	1
							C	TIOB2	I/O	3
H12	VDDIOP1	GPIO	PD15	I/O	–	–	A	CANRX3	I	1	PIO, I, PU, ST
							B	FLEXCOM5_IO3	I/O	1
							C	TCLK2	I	3
E18	VDDIOP1	GPIO	PD16	I/O	–	–	A	CANTX4	O	1	PIO, I, PU, ST
E18	VDDIOP1	GPIO	PD16	I/O	–	–	B	FLEXCOM5_IO0	I/O	1	PIO, I, PU, ST
H13	VDDIOP1	GPIO	PD17	I/O	–	–	A	CANRX4	I	1	PIO, I, PU, ST
H13	VDDIOP1	GPIO	PD17	I/O	–	–	B	FLEXCOM5_IO1	I/O	1	PIO, I, PU, ST
H16	VDDGMAC1	GPIO	PD18	I/O	–	–	B	FLEXCOM6_IO0	I/O	4	PIO, I, PU, ST
							C	CANTX1	O	2
							D	PCK4	O	2
F18	VDDGMAC1	GPIO	PD19	I/O	–	–	B	FLEXCOM6_IO1	I/O	4	PIO, I, PU, ST
							C	CANRX1	I	2
							D	PCK2	O	3
J12	VDDGMAC1	GPIO	PD20	I/O	–	–	B	FLEXCOM6_IO2	I/O	4	PIO, I, PU, ST
							C	I2SMCC1_MCK	O	2
							D	PCK3	O	3
H15	VDDGMAC1	GPIO	PD21	I/O	–	–	A	G1_TXCTL/G1_TXEN	O	1,2	PIO, I, PU, ST
							B	FLEXCOM6_IO2	I/O	3
							C	TK1	I/O	1
F19	VDDGMAC1	GPIO	PD22	I/O	–	–	A	G1_TX0	O	1,2	PIO, I, PU, ST
							B	FLEXCOM6_IO3	I/O	3,4
							C	TF1	I/O	1
G18	VDDGMAC1	GPIO	PD23	I/O	–	–	A	G1_TX1	O	1,2	PIO, I, PU, ST
							B	FLEXCOM6_IO4	O	3,4
							C	TD1	O	1
G19	VDDGMAC1	GPIO	PD24	I/O	–	–	A	G1_RXCTL/G1_CRSDV	I	1,2	PIO, I, PU, ST
							B	FLEXCOM6_IO0	I/O	3
							C	RD1	I	1
							E	PDMC0_DS1	I	3
K9	VDDGMAC1	GPIO	PD25	I/O	–	–	A	G1_MDC	O	1,2	PIO, I, PU, ST
							B	FLEXCOM6_IO1	I/O	3
							C	RK1	I/O	1
							E	PDMC0_CLK	O	3
D19	VDDGMAC1	GPIO	PD26	I/O	–	–	A	G1_MDIO	I/O	1,2	PIO, I, PU, ST
							B	FLEXCOM7_IO4	O	2
							C	RF1	I/O	1
							D	I2SMCC1_DIN2	I	2
							E	PDMC0_DS0	I	3
K10	VDDGMAC1	GPIO	PD27	I/O	–	–	A	G1_RX0	I	1,2	PIO, I, PU, ST
							B	FLEXCOM7_IO0	I/O	2
							C	SPDIF_RX	I	1
							D	I2SMCC1_DIN3	I	2
C19	VDDGMAC1	GPIO	PD28	I/O	–	–	A	G1_RX1	I	1,2	PIO, I, PU, ST
							B	FLEXCOM7_IO1	I/O	2
							C	SPDIF_TX	O	1
							D	I2SMCC1_DIN1	I	2
H18	VDDGMAC1	GPIO	PD29	I/O	–	–	A	G1_REFCK/G1_TXCK	I/O	2,1	PIO, I, PU, ST
							B	FLEXCOM7_IO2	I/O	2
							C	I2SMCC1_DOUT3	O	2
B19	VDDGMAC1	GPIO	PD30	I/O	–	–	A	G1_RX2	I	1	PIO, I, PU, ST
							B	FLEXCOM7_IO3	I/O	2
							C	I2SMCC1_DOUT1	O	2
							D	PDMC1_DS1	I	3
							E	G1_RXER	I	2
F20	VDDGMAC1	GPIO	PD31	I/O	–	–	A	G1_RX3	I	1	PIO, I, PU, ST
							B	FLEXCOM5_IO4	O	2
							C	I2SMCC1_DOUT2	O	2
							D	PDMC1_DS0	I	3
H17	VDDGMAC1	GPIO	PE0	I/O	–	–	A	G1_TX2	O	1	PIO, I, PU, ST
							B	FLEXCOM5_IO2	I/O	2
							C	I2SMCC1_DIN0	I	2
							D	PDMC1_CLK	O	3
G20	VDDGMAC1	GPIO	PE1	I/O	–	–	A	G1_TX3	O	1	PIO, I, PU, ST
							B	FLEXCOM5_IO3	I/O	2
							C	I2SMCC1_WS	I/O	2
							D	PDMC0_DS1	I	4
K12	VDDGMAC1	GPIO	PE2	I/O	–	–	A	G1_RXCK	I	1	PIO, I, PU, ST
							B	FLEXCOM5_IO1	I/O	2
							C	I2SMCC1_CK	I/O	2
							D	PDMC0_CLK	O	4
D20	VDDGMAC1	GPIO	PE3	I/O	–	–	A	G1_TSUCOMP	O	1,2	PIO, I, PU, ST
							B	FLEXCOM5_IO0	I/O	2
							C	I2SMCC1_DOUT0	O	2
							D	PDMC0_DS0	I	4
AA13	VDDLVDS	GPIO	PE4	I/O	LVDS_A0M	O	A	LCDC_DAT0	O	1,2	PIO, I, PU, ST
							B	FLEXCOM2_IO2	I/O	1
							C	PWML0	O	2
							D	TIOA3	I/O	1
							E	I2SMCC0_DIN1	I	2
Y13	VDDLVDS	GPIO	PE5	I/O	LVDS_A0P	O	A	LCDC_DAT1	O	1,2	PIO, I, PU, ST
							B	FLEXCOM2_IO3	I/O	1
							C	PWMH0	O	2
							D	TIOB3	I/O	1
							E	I2SMCC0_DIN2	I	2
AA15	VDDLVDS	GPIO	PE6	I/O	LVDS_A1M	O	A	LCDC_DAT2	O	1,2	PIO, I, PU, ST
							B	FLEXCOM2_IO4	O	1
							C	PWML1	O	2
							D	TCLK3	I	1
							E	I2SMCC0_DIN3	I	2
Y15	VDDLVDS	GPIO	PE7	I/O	LVDS_A1P	O	A	LCDC_DAT3	O	1,2	PIO, I, PU, ST
							B	FLEXCOM2_IO5	O	1
							C	PWMH1	O	2
							D	TIOA4	I/O	1
							E	I2SMCC0_DOUT1	O	2
AA16	VDDLVDS	GPIO	PE8	I/O	LVDS_A2M	O	A	LCDC_DAT4	O	1,2	PIO, I, PU, ST
							B	FLEXCOM2_IO0	I/O	1
							C	PWML2	O	2
							D	TIOB4	I/O	1
							E	I2SMCC0_CK	I/O	2
Y16	VDDLVDS	GPIO	PE9	I/O	LVDS_A2P	O	A	LCDC_DAT5	O	1,2	PIO, I, PU, ST
							B	FLEXCOM2_IO1	I/O	1
							C	PWMH2	O	2
							D	TCLK4	I	1
							E	I2SMCC0_WS	I/O	2
AA19	VDDLVDS	GPIO	PE10	I/O	LVDS_A3M	O	A	LCDC_DAT6	O	1,2	PIO, I, PU, ST
							B	FLEXCOM2_IO6	O	1
							C	PWML3	O	2
							D	TIOA5	I/O	1
							E	I2SMCC0_DOUT2	O	2
Y19	VDDLVDS	GPIO	PE11	I/O	LVDS_A3P	O	A	LCDC_DAT7	O	1,2	PIO, I, PU, ST
							C	PWMH3	O	2
							D	TIOB5	I/O	1
							E	I2SMCC0_DOUT3	O	2
AA18	VDDLVDS	GPIO	PE12	I/O	LVDS_CLK1M	O	A	LCDC_DEN	O	1,2	PIO, I, PU, ST
							B	PCK3	O	4
							C	PWMEXTRG0	I	2
							D	TCLK5	I	1
							E	I2SMCC0_DIN0	I	2
Y18	VDDLVDS	GPIO	PE13	I/O	LVDS_CLK1P	O	A	LCDC_PCK	O	1,2	PIO, I, PU, ST
							B	PCK4	O	3
							C	PWMEXTRG1	I	2
							E	I2SMCC0_DOUT0	O	2
D2	VDDIN33	Analog input	ADVREFP	I	–	–	–	–	–	–	–
G7	VDDIN33	power	VDDIN33	I	–	–	–	–	–	–	–
G5	GNDIN33	ground	GNDIN33	I	–	–	–	–	–	–	–
E7	GNDANA	ground	GNDANA	I	–	–	–	–	–	–	–
H1	GNDANA	ground	GNDANA	I	–	–	–	–	–	–	–
E1	GNDANA	ground	GNDANA	I	–	–	–	–	–	–	–
V9	GNDANA	ground	GNDANA	I	–	–	–	–	–	–	–
T13	VDDIOP0	power	VDDIOP0	I	–	–	–	–	–	–	–
L19	VDDGMAC0	power	VDDGMAC0	I	–	–	–	–	–	–	–
C17	VDDIOP1	power	VDDIOP1	I	–	–	–	–	–	–	–
H19	VDDGMAC1	power	VDDGMAC1	I	–	–	–	–	–	–	–
A1	GND	ground	GND	I	–	–	–	–	–	–	–
A11	GND	ground	GND	I	–	–	–	–	–	–	–
A14	GND	ground	GND	I	–	–	–	–	–	–	–
A17	GND	ground	GND	I	–	–	–	–	–	–	–
A21	GND	ground	GND	I	–	–	–	–	–	–	–
D9	GND	ground	GND	I	–	–	–	–	–	–	–
D13	GND	ground	GND	I	–	–	–	–	–	–	–
E15	GND	ground	GND	I	–	–	–	–	–	–	–
E21	GND	ground	GND	I	–	–	–	–	–	–	–
F16	GND	ground	GND	I	–	–	–	–	–	–	–
G15	GND	ground	GND	I	–	–	–	–	–	–	–
G17	GND	ground	GND	I	–	–	–	–	–	–	–
E5	VDDANA	power	VDDANA	I	–	–	–	–	–	–	–
J6	VDDANA	power	VDDANA	I	–	–	–	–	–	–	–
E3	VDDANA	power	VDDOUT25	O	–	–	–	–	–	–	–
W14	VDDANA	power	VDDIN25	I	–	–	–	–	–	–	–
AA9	GND	ground	GND	I	–	–	–	–	–	–	–
B2	VDDCORE	power	VDDCORE	I	–	–	–	–	–	–	–
F6	VDDCORE	power	VDDCORE	I	–	–	–	–	–	–	–
F15	VDDCORE	power	VDDCORE	I	–	–	–	–	–	–	–
J4	GND	ground	GND	I	–	–	–	–	–	–	–
J9	VDDCORE	power	VDDCORE	I	–	–	–	–	–	–	–
J13	VDDCORE	power	VDDCORE	I	–	–	–	–	–	–	–
J16	VDDCORE	power	VDDCORE	I	–	–	–	–	–	–	–
N13	VDDCORE	power	VDDCORE	I	–	–	–	–	–	–	–
N16	VDDCORE	power	VDDCORE	I	–	–	–	–	–	–	–
T15	VDDCORE	power	VDDCORE	I	–	–	–	–	–	–	–
U16	VDDCORE	power	VDDCORE	I	–	–	–	–	–	–	–
U17	VDDCORE	power	VDDCORE	I	–	–	–	–	–	–	–
U19	VDDCORE	power	VDDCORE	I	–	–	–	–	–	–	–
V19	VDDCORE	power	VDDCORE	I	–	–	–	–	–	–	–
B20	VDDCPU	power	VDDCPU	I	–	–	–	–	–	–	–
E16	VDDCPU	power	VDDCPU	I	–	–	–	–	–	–	–
E17	VDDCPU	power	VDDCPU	I	–	–	–	–	–	–	–
E19	VDDCPU	power	VDDCPU	I	–	–	–	–	–	–	–
F17	VDDCPU	power	VDDCPU	I	–	–	–	–	–	–	–
H3	VDDCORE	power	VDDCORE	I	–	–	–	–	–	–	–
H8	GND	ground	GND	I	–	–	–	–	–	–	–
H14	GND	ground	GND	I	–	–	–	–	–	–	–
H21	GND	ground	GND	I	–	–	–	–	–	–	–
J18	GND	ground	GND	I	–	–	–	–	–	–	–
K11	GND	ground	GND	I	–	–	–	–	–	–	–
L1	GND	ground	GND	I	–	–	–	–	–	–	–
L11	GND	ground	GND	I	–	–	–	–	–	–	–
L15	GND	ground	GND	I	–	–	–	–	–	–	–
L21	GND	ground	GND	I	–	–	–	–	–	–	–
N4	GND	ground	GND	I	–	–	–	–	–	–	–
N18	GND	ground	GND	I	–	–	–	–	–	–	–
P1	GND	ground	GND	I	–	–	–	–	–	–	–
P8	GND	ground	GND	I	–	–	–	–	–	–	–
P14	GND	ground	GND	I	–	–	–	–	–	–	–
P21	GND	ground	GND	I	–	–	–	–	–	–	–
R5	GND	ground	GND	I	–	–	–	–	–	–	–
R7	GND	ground	GND	I	–	–	–	–	–	–	–
AA11	GND	ground	GND	I	–	–	–	–	–	–	–
W11	VDDLVDS	power	VDDLVDS	I	–	–	–	–	–	–	–
L7	GNDUTMI	ground	GNDUTMI	I	–	–	–	–	–	–	–
L3	VDDUTMI	power	VDDUTMI	I	–	–	–	–	–	–	–
F2	VDDUTMI	–	HHSDPA	I/O	–	–	–	–	–	–	–
F1	VDDUTMI	–	HHSDMA	I/O	–	–	–	–	–	–	–
G2	VDDUTMI	–	HHSDPB	I/O	–	–	–	–	–	–	–
G1	VDDUTMI	–	HHSDMB	I/O	–	–	–	–	–	–	–
J2	VDDUTMI	–	HHSDPC	I/O	–	–	–	–	–	–	–
J1	VDDUTMI	–	HHSDMC	I/O	–	–	–	–	–	–	–
K7	VDDUTMI	Analog input	HHSRTUNE	I	–	–	–	–	–	–	–
AA5	VDDIODDR	power	VDDIODDR	I	–	–	–	–	–	–	–
M11	VDDIODDR	power	VDDIODDR	I	–	–	–	–	–	–	–
N6	VDDIODDR	power	VDDIODDR	I	–	–	–	–	–	–	–
N9	VDDIODDR	power	VDDIODDR	I	–	–	–	–	–	–	–
N12	VDDIODDR	power	VDDIODDR	I	–	–	–	–	–	–	–
P3	VDDIODDR	power	VDDIODDR	I	–	–	–	–	–	–	–
P13	VDDIODDR	power	VDDIODDR	I	–	–	–	–	–	–	–
T6	VDDIODDR	power	VDDIODDR	I	–	–	–	–	–	–	–
T7	VDDIODDR	power	VDDIODDR	I	–	–	–	–	–	–	–
T9	VDDIODDR	power	VDDIODDR	I	–	–	–	–	–	–	–
U3	VDDIODDR	power	VDDIODDR	I	–	–	–	–	–	–	–
U5	VDDIODDR	power	VDDIODDR	I	–	–	–	–	–	–	–
U6	VDDIODDR	power	VDDIODDR	I	–	–	–	–	–	–	–
W8	VDDIODDR	power	VDDIODDR	I	–	–	–	–	–	–	–
Y2	VDDIODDR	power	VDDIODDR	I	–	–	–	–	–	–	–
R11	GND	ground	GND	I	–	–	–	–	–	–	–
R17	GND	ground	GND	I	–	–	–	–	–	–	–
T5	GND	ground	GND	I	–	–	–	–	–	–	–
T17	GND	ground	GND	I	–	–	–	–	–	–	–
U1	GND	ground	GND	I	–	–	–	–	–	–	–
U7	GND	ground	GND	I	–	–	–	–	–	–	–
U21	GND	ground	GND	I	–	–	–	–	–	–	–
V13	GND	ground	GND	I	–	–	–	–	–	–	–
W5	GND	ground	GND	I	–	–	–	–	–	–	–
AA1	GND	ground	GND	I	–	–	–	–	–	–	–
AA8	GND	ground	GND	I	–	–	–	–	–	–	–
AA14	GND	ground	GND	I	–	–	–	–	–	–	–
AA17	GND	ground	GND	I	–	–	–	–	–	–	–
AA21	GND	ground	GND	I	–	–	–	–	–	–	–
Y1	VDDIODDR	Analog input	DDR_VREF	I	–	–	–	–	–	–	–
N2	VDDIODDR	–	DDR_D0	I/O	–	–	–	–	–	–	–
M7	VDDIODDR	–	DDR_D1	I/O	–	–	–	–	–	–	–
R3	VDDIODDR	–	DDR_D2	I/O	–	–	–	–	–	–	–
M8	VDDIODDR	–	DDR_D3	I/O	–	–	–	–	–	–	–
T2	VDDIODDR	–	DDR_D4	I/O	–	–	–	–	–	–	–
N8	VDDIODDR	–	DDR_D5	I/O	–	–	–	–	–	–	–
T1	VDDIODDR	–	DDR_D6	I/O	–	–	–	–	–	–	–
N7	VDDIODDR	–	DDR_D7	I/O	–	–	–	–	–	–	–
Y7	VDDIODDR	–	DDR_D8	I/O	–	–	–	–	–	–	–
AA4	VDDIODDR	–	DDR_D9	I/O	–	–	–	–	–	–	–
Y9	VDDIODDR	–	DDR_D10	I/O	–	–	–	–	–	–	–
Y3	VDDIODDR	–	DDR_D11	I/O	–	–	–	–	–	–	–
AA7	VDDIODDR	–	DDR_D12	I/O	–	–	–	–	–	–	–
AA3	VDDIODDR	–	DDR_D13	I/O	–	–	–	–	–	–	–
W7	VDDIODDR	–	DDR_D14	I/O	–	–	–	–	–	–	–
W3	VDDIODDR	–	DDR_D15	I/O	–	–	–	–	–	–	–
W6	VDDIODDR	–	DDR_A0	O	–	–	–	–	–	–	–
P6	VDDIODDR	–	DDR_A1	O	–	–	–	–	–	–	–
V5	VDDIODDR	–	DDR_A2	O	–	–	–	–	–	–	–
V6	VDDIODDR	–	DDR_A3	O	–	–	–	–	–	–	–
R6	VDDIODDR	–	DDR_A4	O	–	–	–	–	–	–	–
W4	VDDIODDR	–	DDR_A5	O	–	–	–	–	–	–	–
P7	VDDIODDR	–	DDR_A6	O	–	–	–	–	–	–	–
W2	VDDIODDR	–	DDR_A7	O	–	–	–	–	–	–	–
L8	VDDIODDR	–	DDR_A8	O	–	–	–	–	–	–	–
V4	VDDIODDR	–	DDR_A9	O	–	–	–	–	–	–	–
T3	VDDIODDR	–	DDR_A10	O	–	–	–	–	–	–	–
M9	VDDIODDR	–	DDR_A11	O	–	–	–	–	–	–	–
P5	VDDIODDR	–	DDR_A12	O	–	–	–	–	–	–	–
V2	VDDIODDR	–	DDR_A13	O	–	–	–	–	–	–	–
L9	VDDIODDR	–	DDR_A14	O	–	–	–	–	–	–	–
R4	VDDIODDR	–	DDR_A15	O	–	–	–	–	–	–	–
U4	VDDIODDR	–	DDR_CLK	O	–	–	–	–	–	–	–
T4	VDDIODDR	–	DDR_CLKN	O	–	–	–	–	–	–	–
V3	VDDIODDR	–	DDR_CKE	O	–	–	–	–	–	–	–
AA2	VDDIODDR	Analog input	DDR_ZQ	O	–	–	–	–	–	–	–
V7	VDDIODDR	–	DDR_CSN	O	–	–	–	–	–	–	–
N10	VDDIODDR	–	DDR_WEN	O	–	–	–	–	–	–	–
U8	VDDIODDR	–	DDR_RASN	O	–	–	–	–	–	–	–
T8	VDDIODDR	–	DDR_CASN	O	–	–	–	–	–	–	–
N1	VDDIODDR	–	DDR_DQM0	O	–	–	–	–	–	–	–
Y4	VDDIODDR	–	DDR_DQM1	O	–	–	–	–	–	–	–
R1	VDDIODDR	–	DDR_DQS0	I/O	–	–	–	–	–	–	–
Y6	VDDIODDR	–	DDR_DQS1	I/O	–	–	–	–	–	–	–
R2	VDDIODDR	–	DDR_DQSN0	I/O	–	–	–	–	–	–	–
AA6	VDDIODDR	–	DDR_DQSN1	I/O	–	–	–	–	–	–	–
V8	VDDIODDR	–	DDR_BA0	O	–	–	–	–	–	–	–
P4	VDDIODDR	–	DDR_BA1	O	–	–	–	–	–	–	–
R8	VDDIODDR	–	DDR_BA2	O	–	–	–	–	–	–	–
W1	VDDIODDR	–	DDR_ODT	O	–	–	–	–	–	–	–
V1	VDDIODDR	–	DDR_RESETN	I	–	–	–	–	–	–	–
T16	VDDDPHY	power	VDDDPHY	I	–	–	–	–	–	–	–
R15	GNDDPHY	ground	GNDDPHY	I	–	–	–	–	–	–	–
U15	GNDDPHY	ground	GNDDPHY	I	–	–	–	–	–	–	–
V20	VDDDPHY	–	MIPI_CLKN	O	–	–	–	–	–	–	–
V21	VDDDPHY	–	MIPI_CLKP	O	–	–	–	–	–	–	–
Y20	VDDDPHY	–	MIPI_DN0	O	–	–	–	–	–	–	–
Y21	VDDDPHY	–	MIPI_DP0	O	–	–	–	–	–	–	–
W20	VDDDPHY	–	MIPI_DN1	O	–	–	–	–	–	–	–
W21	VDDDPHY	–	MIPI_DP1	O	–	–	–	–	–	–	–
T20	VDDDPHY	–	MIPI_DN2	O	–	–	–	–	–	–	–
T21	VDDDPHY	–	MIPI_DP2	O	–	–	–	–	–	–	–
R20	VDDDPHY	–	MIPI_DN3	O	–	–	–	–	–	–	–
R21	VDDDPHY	–	MIPI_DP3	O	–	–	–	–	–	–	–
V18	VDDDPHY	Analog input	MIPI_REXT	I	–	–	–	–	–	–	–
W17	VDDSDMMC0	power	VDDSDMMC0	I	–	–	–	–	–	–	–
F9	VDDSDMMC1	power	VDDSDMMC1	I	–	–	–	–	–	–	–
R16	VDDSDMMC0	Analog input	SDMMC0_CAL	I	–	–	–	–	–	–	–
B13	VDDSDMMC1	Analog input	SDMMC1_CAL	I	–	–	–	–	–	–	–
F13	VDDSDMMC2	power	VDDSDMMC2	I	–	–	–	–	–	–	–
E14	VDDSDMMC2	Analog input	SDMMC2_CAL	I	–	–	–	–	–	–	–
G11	GNDBAT	ground	GNDBAT	I	–	–	–	–	–	–	–
E8	VBAT	power	VBAT	I	–	–	–	–	–	–	–
J10	VBAT	PIOBU	PIOBU0⁽⁵⁾	I/O	–	–	–	–	–	–	PU⁽⁶⁾
A5	VBAT	PIOBU	PIOBU1⁽⁵⁾	I/O	–	–	–	–	–	–	PU⁽⁶⁾
D8	VBAT	PIOBU	PIOBU2⁽⁵⁾	I/O	–	–	–	–	–	–	PU⁽⁶⁾
A4	VBAT	PIOBU	PIOBU3⁽⁵⁾	I/O	–	–	–	–	–	–	PD⁽⁶⁾
B7	VDDIN33	–	XIN	I	–	–	–	–	–	–	–
A7	VDDIN33	–	XOUT	O	–	–	–	–	–	–	–
A9	VBAT	–	XIN32	I	–	–	–	–	–	–	–
B9	VBAT	–	XOUT32	O	–	–	–	–	–	–	–
G9	VBAT	–	TST	I	–	–	–	–	–	–	PD
H10	VBAT	–	JTAGSEL	I	–	–	–	–	–	–	PD
A8	VBAT	–	WKUP0	I	–	–	–	–	–	–	–
B4	VBAT	–	SHDN	O	–	–	–	–	–	–	–
D3	VDDIN33	–	NRST	I	–	–	–	–	–	–	PU
E4	VDDIN33	–	NRST_OUT	O	–	–	–	–	–	–	OD⁽⁷⁾
K8	VDDIN33	GPIO	AUDIOCLK	O	–	–	–	–	–	–	–
A6	VBAT	–	LPM	O	–	–	–	–	–	–	–
P19	VDDQSPI0	power	VDDQSPI0	I	–	–	–	–	–	–	–
M13	VDDQSPI0	Analog input	QSPI0_CAL	I	–	–	–	–	–	–	–
C7	GND	ground	GND	I	–	–	–	–	–	–	–
H9	GND	ground	GND	I	–	–	–	–	–	–	–
B6	GND	ground	GND	I	–	–	–	–	–	–	–
C4	GND	ground	GND	I	–	–	–	–	–	–	–
Note: I/Os for each peripheral are grouped into I/O sets, listed in the column "I/O Set." For all peripherals, use I/Os that belong to the same I/O set. Timings can be unpredictable when I/Os from different I/O sets are mixed. When using an I/O line with the Analog-to-Digital Converter (ADC) or with the Analog Comparator Controller (ACC), the PIO line configuration (pull-up, pull-down) programmed before assigning this line to the ADC or ACC peripheral is not modified by this peripheral. Refer to I/O Characteristics in the Electrical Characteristics section for the definition of I/Os. PU=Pull-Up, PD=Pull-Down, HiZ=High Impedance, ST=Schmitt Trigger. PIOBU0, PIOBU1, PIOBU2, and PIOBU3 are respectively used as WKUP2, WKUP3, WKUP4 and WKUP5 signal for the product wake-up or tamper feature. This is the PIOBU state after VBAT power-up. If programmed to another value, this value is maintained as long as VBAT is not removed. Open-drain output requires an external resistor.