6.2.6.9.2 Pixel Striding

At each pixel, the DMA address counter points to the next pixel address. The channel DMA current address value is added to the PSTRIDE field and then updated. If PSTRIDE is set to 0, the DMA address register remains unchanged. The PSTRIDE field of the channel configuration register is aligned to the pixel size boundary. The PSTRIDE field is a two’s complement number. The following formula applies at each pixel and indicates how the DMA controller computes the next pixel address. The function Sizeof() returns the number of bytes required to store a pixel.

The Base Layer does not support pixel striding.

For overlays, pixel striding is not supported for the following modes:

• YCrCb 4:2:2 packed modes:
  • 16BPP_YCBCR_MODE0
  • 16BPP_YCBCR_MODE1
  • 16BPP_YCBCR_MODE2
  • 16BPP_YCBCR_MODE3
• CLUT modes less than 8bpp
  • CLUT_1BPP
  • CLUT_2BPP
  • CLUT_4BPP