7.7.5.14 ASRC Built-In Self Test for Embedded Memories

The ASRC embeds ROM and RAM memories.

A functional check of these memories may be performed prior to enabling one or more audio channels.

The memory check procedure can be started only when ASRC_MR.ASRCENx=0.

The ROM content check uses a CRC-24.

The embedded RAM check algorithm is divided in four phases:

  • The first phase writes alternate patterns for each consecutive address (@0x0 = 0xA5A5..A5, @0x1 = 0x5A5A..5A, etc).
  • The second phase reads and checks the values written in the first phase.
  • The third phase writes alternate patterns for each consecutive address (@0x0 = 0x5A5A..5A, @0x1 = 0xA5A5..A5, etc) in the opposite way compared to the first phase.
  • The fourth phase reads and checks the values written in the third phase.

When the memory procedure elapses, the flags ASRC_ISRx.EOMCP=1. The flags share the same event source and are duplicated on all ASRC_ISRx.

Any memory error is reported in ASRC_ESR. A ROM content error is signaled when ASRC_ESR.ROMS=1; a RAM error is signaled when ASRC_ESR.SRAMS=1. These two status bits are cleared at the start of a memory check procedure and remain high in case of persistent error.

When not all channels are in use, or to determine which channel can be affected by a memory error, the ASRC memory check procedure offers the capability to restrict the memory check to memories allocated to selected DSP channels. To determine which channel has a faulty memory, the check procedure must be repeated for each DSP channel. The memories of all the DSP channels are checked when ASRC_CR.DSPMEMSEL=0 and ASRC_CR.MEMCHECK=1. When ASRC_CR.DSPMEMSEL>0 and ASRC_CR.MEMCHECK=1, only memories of the selected DSP are checked.

Note: It is possible to determine a failure in memories of DSP0/1/3 with a single step check sequence, whereas a hardware failure of DSP2 memories can be performed by first starting a check of all memories (DSPMEMSEL=0), then starting the DSP0/1/3 memory checks. When SRAMS=1 for DSPMEMSEL=0 and SRAMS=0 for DSPMEMSEL>0, then the hardware failure exists in memories associated to DSP2.

It is also possible to check the ability of the verify status flags (ASRC_ESR.ROMS/SRAMS) to rise in case of error by emulating a memory read failure during the check read phases.

To emulate a read failure, ASRC_FIR.F0 must be written to ‘1’ prior to starting the memory check procedure. The memory check period elapses with ASRC_ESR.ROMS= ASRC_ESR.SRAMS=1. To clear these bits (assuming no real memory failure), ASRC_FIR.F0 must be written to ‘0’ followed by an ASRC_WPSR read to clear the flag SECE and a new memory check procedure must be started by writing ASRC_CR.MEMCHECK=1.