7.7.5.4 Embedded Digital PLL

Each DSP embeds a digital PLL (DPLL) for precise estimation of the sampling points.

The embedded DPLL precisely computes the ratio between the input and the output sampling rates to obtain a high-quality output signal.

The DSP must be disabled (ASRC_MR.ASRCENx=0) if both input and output sampling rates are not established, as the DPLL continuously computes the sampling rate difference between the input and the output audio streams.

If sampling rates are provided by an external trigger signal (ASRC_TRIG.TRIGSELINx=0 or ASRC_TRIG.TRIGSELOUTx=0) and the signal is lost, the DPLL unlocks and the root cause is reported on two separate bits. DPLL can unlock due to the absence of input sampling frequency, an absence of output sampling frequency or both. Thus two separate bits (ASRC_ISRx.FSOUTLOSS, ASRC_ISRx.FSINLOSS) ease the identification of the unlock.