2.2.3.6 UDDRC

The five ports are configured with PCFGQOS0_[port number], PCFGQOS1_[port number], PCFGWQOS0_[port number], PCFGWQOS1_[port number].

The following table summarizes how to program Outstanding Capability in each applicable section.

Table 2-10. Outstanding Capability Programming
InstanceAXI Outstanding Management
DMA0XDMAC0_GCFG.WRHP, XDMAC0_GCFG.WRMP, XDMAC0_GCFG.WRLP, XDMAC0_GCFG.RDHP, XDMAC0_GCFG.RDMP, XDMAC0_GCFG.RDSP
DMA1XDMAC1_GCFG.WRHP, XDMAC1_GCFG.WRMP, XDMAC1_GCFG.WRLP, XDMAC1_GCFG.RDHP, XDMAC1_GCFG.RDMP, XDMAC1_GCFG.RDSP
DMA2XDMAC2_GCFG.WRHP, XDMAC2_GCFG.WRMP, XDMAC2_GCFG.WRLP, XDMAC2_GCFG.RDHP, XDMAC2_GCFG.RDMP, XDMAC2_GCFG.RDSP
GMAC0GMAC0_AMP register
GMAC1GMAC1_AMP register

The following table summarizes how to program QoS in each applicable section.

Table 2-11. Quality of Service Programming
InstanceQoS Management

Default Value

Transaction Outstanding Latency Regulation in NICGPV

CPUASIB[0] in NICGPV(1)0–
DMA0, per channelQoS in XDMAC0_CNDC[channel number] registers0–
DMA1, per channelQoS in XDMAC1_CNDC[channel number] registers0–
DMA2, per channelQoS in XDMAC2_CNDC[channel number] registers0X
GMAC0QOS in GMAC_QOS_CFG0 and GMAC_QOS_CFG1 registers0X
GMAC1QOS in GMAC_QOS_CFG0 and GMAC_QOS_CFG1 registers0X
SDMMC0Peripheral for descriptors, in SDMMC0_ACR register0X
SDMMC1Peripheral for descriptors, in SDMMC1_ACR register0X
SDMMC2Peripheral for descriptors, in SDMMC2_ACR register0X
DDR port, per portUDDRC in PCFGQOS0_[port number], PCFGQOS1_[port number], PCFGWQOS0_[port number], PCFGWQOS1_[port number] registers0–
AHB matrix hosts (including CPU)

MATRIX_PRAS[port number]

MATRIX_PRBS[port number]

0

2

–
Note:
  1. This QoS is not propagated to the AHB matrix through the M0 port.

For details, refer to the relevant peripheral sections and to NIC-400 Global Programmer’s View (NICGPV), Bus Matrix (MATRIX) and Special Function Registers (SFR).