Memory Automatic Low-Power Control in Active State
Two SFR registers are available to configure the behavior of the automatic memory power state switch:
- SFR_DISABLE_SD_CFG: enables/disables the automatic power state control for each peripheral. When disabled, the memory remains in its Normal state regardless of the peripheral clock status (on or off). Enabled by default at reset.
- SFR_CLEAR_ONLY_SD_CFG: for
each peripheral, use this register to choose between the following low-power memory
policies:
- The memory Low-Power state is always controlled by the peripheral clock status (default behavior at reset).
- The memory remains in the Normal state after the first peripheral clock activation.
For all peripherals, SFR_DISABLE_SD_CFG has priority over SFR_CLEAR_ONLY_SD_CFG. If SFR_DISABLE_SD_CFG=1, the memory remains in Normal state, whatever the value of SFR_CLEAR_ONLY_SD_CFG or the peripheral clock status (on or off). See the following table.
| SFR_CLEAR_ONLY_SD_CFGx | |||
|---|---|---|---|
| 0 | 1 | ||
| SFR_DISABLE_SD_CFG | 0 |
Memories in Normal state when peripheral clock enabled Memories shut down when peripheral clock disabled | Memories remain in Normal state after first peripheral clock enable |
| 1 | Memories always ON | ||
In Active state, when a peripheral is clock gated, its embedded memories enter Shutdown state.