2.2.1.1 AXI Subsystem

The AXI subsystem is comprised of:

  • CSS — CPU System and Security matrix
  • CHS — CPU High Speed matrix
  • APS — APB Client matrix
  • AXM — AXI Hosts matrix
  • ISS — AXI Image Subsystem

AXI matrixes are based on NIC-400 r1p1 (by Arm Ltd.) and no settings are controlled by software. The respective hardware configurations used are described in the following sections. The default software configuration has been intensively tested and leads to best results in any conditions.

For complete details on the NIC-400 design, see the Arm specification on http://infocenter.arm.com/help/topic/com.arm.doc.ddi0475h/index.html.

The device embeds Quality of Service management provided by Arm QoS-400 supplement to NIC-400. QoS-400 r1p1 is controlled by software. The respective hardware configurations used are described in the following sections. The default software configuration has been intensively tested and leads to best results in any conditions.

For complete details on the QoS-400, see the Arm specification on http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dsu0026g/index.html

This AXI subsystem (NICGPV) is connected to peripherals and to an AHB matrix (MATRIX) described below.

The following tables summarize the AXI matrix hosts and clients.

Table 2-3. AXI Hosts
Host PortPort Name
UDDRC_P0AMIB0
Bridge to HSS M0 CHSAMIB1
ROM/OTP CSSAMIB2
CPKCC CSSAMIB3
APB0 CSSAMIB4
DDRC_P2 APSAMIB5
Bridge to HSS M1 APSAMIB6
APB1+APB4+APB7+APB9+GPU2DC+NICGPV APSAMIB7
APB2 APSAMIB8
APB3 APSAMIB9
APB8 APSAMIB10
APB5+APB9+APB10 APSAMIB11
UDDRC_P4AMIB12
Bridge to HSS M2 AXMAMIB13
Table 2-4. AXI Clients
Client PortPort Name
CPU CHSASIB0
OTP CSSASIB1
XDMAC0 APSASIB2
XDMAC1 APSASIB3
AXI_AP1ASIB4
GMAC0 AXMASIB5
GMAC1 AXMASIB6
SDMMC0 AXMASIB7
SDMMC1 AXMASIB8
SDMMC2 AXMASIB9
XDMAC2 AXMASIB10
Table 2-5. AXI Image Subsystem Hosts
Host PortPort Name
GPU2DCAMIB0
LCDCAMIB1
Table 2-6. AXI Image Subsystem Clients
Client PortPort Name
UDDRC_P3ASIB0