11.1.7.1.2 QSPI Timings

For the QSPI0 instance, the timings shown in the tables below are provided in the following domains:

1.8V domain: VDDQSPI0 from 1.7V to 1.9V, maximum external capacitor: 10 pF, drive: 01 (Type A)
3.3V domain: VDDQSPI0 from 3.0V to 3.6V, maximum external capacitor: 10 pF, drive: 01 (Type A)

For the QSPI1 instance, the timings shown in the table below are provided in the following domains:

1.8V domain: VDDQSPI0 from 1.7V to 1.9V, maximum external capacitor: 10 pF, DRV: 1, SR: 0
3.3V domain: VDDQSPI0 from 3.0V to 3.6V, maximum external capacitor: 10 pF, DRV: 0, SR: 0

Table 11-27. QSPI Timings in Single Data Rate Mode (STR)
Symbol	Parameter	Conditions	Min	Max	Unit
f_QSCK	QSCK maximum frequency	–	–	133	MHz
QSPI₀	QIOx data in to QSCK falling edge (input setup time)	–	1	–	ns
QSPI₁	QIOx data in to QSCK falling edge (input hold time)	–	1	–	ns
QSPI₂	QSCK falling edge to QIOx delay	–	0	1	ns

Table 11-28. QSPI Timings in Double Data Rate Mode (DTR)
Symbol	Parameter	Conditions	Min	Max	Unit
f_QSPI	QSCK operating frequency	–	–	90	MHz
t_{QSCK_MIN}	Minimum SPCK period	–	11.1	–	ns
QSPI₆	CS low before QSCK edge (rising or falling)⁽¹⁾	–	2	–	ns
QSPI₇	QSCK edge (rising or falling) to CS high⁽²⁾	–	0	1	ns
QSPI₈	QIOx input data setup to QSCK edge (rising or falling)	–	1	–	ns
QSPI₉	QIOx input data hold after QSCK edge (rising or falling)	–	1	–	ns
QSPI₁₀	QSCK edge (rising or falling) to QIOx delay	–	0	1	ns

Note:

Refer to DLYCS and DLYBS descriptions in Quad Serial Peripheral Interface (QSPI) for more configuration details.
Refer to DLYBCT description in Quad Serial Peripheral Interface (QSPI) for more configuration details.

Table 11-29. QSPI Timings in DTR Mode with Data Strobe (DQS) (QSPI0 Only)
Symbol	Parameter	Conditions	Min	Max	Unit
f_QSPI	QSCK operating frequency	–	–	200	MHz
t_{QSCK_MIN}	Minimum SPCK period	–	5	–	ns
QSPI₁₁	CS low before QSCK edge (rising or falling)⁽¹⁾	–	2	–	ns
QSPI₁₂	QSCK edge (rising or falling) to CS high⁽²⁾	–	0	1	ns
QSPI₁₃	QIOx input skew to DQS edge (rising or falling)	–	-0.8	1.4	ns
QSPI₁₄	QSCK edge (rising or falling) to QIOx delay	–	0	t_QSCK/4 + 0.6	ns

Note:

Refer to DLYCS and DLYBS descriptions in Quad Serial Peripheral Interface (QSPI) for more configuration details.
Refer to DLYBCT description in Quad Serial Peripheral Interface (QSPI) for more configuration details.

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