Introduction
Reference Document
1 Overview
2 CPU and Interconnect
3 Memories
4 System Controller
5 Analog Subsystem
6 Image Subsystem
7 Audio Subsystem
8 Security and Cryptography Subsystem
9 Connectivity Subsystem
- 9.1 Overview
- 9.2 Ethernet MAC (GMAC)
- 9.3 Flexible Serial Communication Controller (FLEXCOM)
  - 9.3.1 Description
  - 9.3.2 Embedded Characteristics
  - 9.3.3 Block Diagram
  - 9.3.4 I/O Lines Description
  - 9.3.5 Product Dependencies
  - 9.3.6 Register Accesses
  - 9.3.7 USART Functional Description
  - 9.3.8 SPI Functional Description
  - 9.3.9 TWI Functional Description
  - 9.3 Register Summary
    - 9.3.1 FLEXCOM Mode Register
      FLEXCOM Mode Register
    - 9.3.2 FLEXCOM Receive Holding Register
      FLEXCOM Receive Holding Register
    - 9.3.3 FLEXCOM Transmit Holding Register
      FLEXCOM Transmit Holding Register
    - 9.3.4 USART Control Register
      USART Control Register
    - 9.3.5 USART Mode Register
      USART Mode Register
    - 9.3.6 USART Interrupt Enable Register (Default Mode)
      USART Interrupt Enable Register (Default Mode)
    - 9.3.7 USART Interrupt Enable Register (LIN_MODE)
      USART Interrupt Enable Register (LIN_MODE)
    - 9.3.8 USART Interrupt Disable Register (Default Mode)
      USART Interrupt Disable Register (Default Mode)
    - 9.3.9 USART Interrupt Disable Register (LIN_MODE)
      USART Interrupt Disable Register (LIN_MODE)
    - 9.3.10 USART Interrupt Mask Register (Default Mode)
      USART Interrupt Mask Register (Default Mode)
    - 9.3.11 USART Interrupt Mask Register (LIN_MODE)
      USART Interrupt Mask Register (LIN_MODE)
    - 9.3.12 USART Channel Status Register (Default Mode)
      USART Channel Status Register (Default Mode)
    - 9.3.13 USART Channel Status Register (LIN_MODE)
      USART Channel Status Register (LIN_MODE)
    - 9.3.14 USART Receive Holding Register (Default Mode)
      USART Receive Holding Register (Default Mode)
    - 9.3.15 USART Receive Holding Register (FIFO Multi Data)
      USART Receive Holding Register (FIFO Multi Data)
    - 9.3.16 USART Transmit Holding Register (Default Mode)
      USART Transmit Holding Register (Default Mode)
    - 9.3.17 USART Transmit Holding Register (FIFO Multi Data)
      USART Transmit Holding Register (FIFO Multi Data)
    - 9.3.18 USART Baud Rate Generator Register
      USART Baud Rate Generator Register
    - 9.3.19 USART Receiver Timeout Register
      USART Receiver Timeout Register
    - 9.3.20 USART Transmitter Timeguard Register
      USART Transmitter Timeguard Register
    - 9.3.21 USART FI DI RATIO Register
      USART FI DI RATIO Register
    - 9.3.22 USART Number of Errors Register
      USART Number of Errors Register
    - 9.3.23 USART IrDA FILTER Register
      USART IrDA FILTER Register
    - 9.3.24 USART Manchester Configuration Register
      USART Manchester Configuration Register
    - 9.3.25 USART LIN Mode Register
      USART LIN Mode Register
    - 9.3.26 USART LIN Identifier Register
      USART LIN Identifier Register
    - 9.3.27 USART LIN Baud Rate Register
      USART LIN Baud Rate Register
    - 9.3.28 USART Comparison Register
      USART Comparison Register
    - 9.3.29 USART FIFO Mode Register
      USART FIFO Mode Register
    - 9.3.30 USART FIFO Level Register
      USART FIFO Level Register
    - 9.3.31 USART FIFO Interrupt Enable Register
      USART FIFO Interrupt Enable Register
    - 9.3.32 USART FIFO Interrupt Disable Register
      USART FIFO Interrupt Disable Register
    - 9.3.33 USART FIFO Interrupt Mask Register
      USART FIFO Interrupt Mask Register
    - 9.3.34 USART FIFO Event Status Register
      USART FIFO Event Status Register
    - 9.3.35 USART Write Protection Mode Register
      USART Write Protection Mode Register
    - 9.3.36 USART Write Protection Status Register
      USART Write Protection Status Register
    - 9.3.37 SPI Control Register
      SPI Control Register
    - 9.3.38 SPI Mode Register
      SPI Mode Register
    - 9.3.39 SPI Receive Data Register (Default Mode)
      SPI Receive Data Register (Default Mode)
    - 9.3.40 SPI Receive Data Register (Multiple Data, 8-bit)
      SPI Receive Data Register (Multiple Data, 8-bit)
    - 9.3.41 SPI Receive Data Register (Multiple Data, 16-bit)
      SPI Receive Data Register (Multiple Data, 16-bit)
    - 9.3.42 SPI Transmit Data Register (Default Mode)
      SPI Transmit Data Register (Default Mode)
    - 9.3.43 SPI Transmit Data Register (Multiple Data, 8- to 16-bit)
      SPI Transmit Data Register (Multiple Data, 8- to 16-bit)
    - 9.3.44 SPI Status Register
      SPI Status Register
    - 9.3.45 SPI Interrupt Enable Register
      SPI Interrupt Enable Register
    - 9.3.46 SPI Interrupt Disable Register
      SPI Interrupt Disable Register
    - 9.3.47 SPI Interrupt Mask Register
      SPI Interrupt Mask Register
    - 9.3.48 SPI Chip Select Register
      SPI Chip Select Register
    - 9.3.49 SPI FIFO Mode Register
      SPI FIFO Mode Register
    - 9.3.50 SPI FIFO Level Register
      SPI FIFO Level Register
    - 9.3.51 SPI Comparison Register
      SPI Comparison Register
    - 9.3.52 SPI Write Protection Mode Register
      SPI Write Protection Mode Register
    - 9.3.53 SPI Write Protection Status Register
      SPI Write Protection Status Register
    - 9.3.54 TWI Control Register (Default Mode)
      TWI Control Register (Default Mode)
    - 9.3.55 TWI Control Register (FIFO_ENABLED)
      TWI Control Register (FIFO_ENABLED)
    - 9.3.56 TWI Host Mode Register
      TWI Host Mode Register
    - 9.3.57 TWI Client Mode Register
      TWI Client Mode Register
    - 9.3.58 TWI Internal Address Register
      TWI Internal Address Register
    - 9.3.59 TWI Clock Waveform Generator Register
      TWI Clock Waveform Generator Register
    - 9.3.60 TWI Status Register (Default Mode)
      TWI Status Register (Default Mode)
    - 9.3.61 TWI Status Register (FIFO ENABLED)
      TWI Status Register (FIFO ENABLED)
    - 9.3.62 TWI Interrupt Enable Register
      TWI Interrupt Enable Register
    - 9.3.63 TWI Interrupt Disable Register
      TWI Interrupt Disable Register
    - 9.3.64 TWI Interrupt Mask Register
      TWI Interrupt Mask Register
    - 9.3.65 TWI Receive Holding Register (Default Mode)
      TWI Receive Holding Register (Default Mode)
    - 9.3.66 TWI Receive Holding Register (FIFO Enabled)
      TWI Receive Holding Register (FIFO Enabled)
    - 9.3.67 TWI Transmit Holding Register (Default Mode)
      TWI Transmit Holding Register (Default Mode)
    - 9.3.68 TWI Transmit Holding Register (FIFO Enabled)
      TWI Transmit Holding Register (FIFO Enabled)
    - 9.3.69 TWI SMBus Timing Register
      TWI SMBus Timing Register
    - 9.3.70 TWI High-Speed Register
      TWI High-Speed Register
    - 9.3.71 TWI Alternative Command Register
      TWI Alternative Command Register
    - 9.3.72 TWI Filter Register
      TWI Filter Register
    - 9.3.73 TWI High-Speed Clock Waveform Generator Register
      TWI High-Speed Clock Waveform Generator Register
    - 9.3.74 TWI Matching Register
      TWI Matching Register
    - 9.3.75 TWI FIFO Mode Register
      TWI FIFO Mode Register
    - 9.3.76 TWI FIFO Level Register
      TWI FIFO Level Register
    - 9.3.77 TWI FIFO Status Register
      TWI FIFO Status Register
    - 9.3.78 TWI FIFO Interrupt Enable Register
      TWI FIFO Interrupt Enable Register
    - 9.3.79 TWI FIFO Interrupt Disable Register
      TWI FIFO Interrupt Disable Register
    - 9.3.80 TWI FIFO Interrupt Mask Register
      TWI FIFO Interrupt Mask Register
    - 9.3.81 TWI Write Protection Mode Register
      TWI Write Protection Mode Register
    - 9.3.82 TWI Write Protection Status Register
      TWI Write Protection Status Register
- 9.4 Quad Serial Peripheral Interface (QSPI)
- 9.5 Secure Digital MultiMedia Card Controller (SDMMC)
- 9.6 Controller Area Network (MCAN)
- 9.7 I3C Controller (I3CC)
- 9.8 Pulse Width Modulation Controller (PWM)
- 9.9 Timer Counter (TC)
10 USB Subsystem
11 Electrical and Mechanical Characteristics
12 Glossary
13 Revision History
Microchip Information

9.3.53 SPI Write Protection Status Register

Name:	FLEX_SPI_WPSR
Offset:	0x4E8
Reset:	0x00000000
Property:	Read-only


Bit	31	30	29	28	27	26	25	24

Access
Reset


Bit	23	22	21	20	19	18	17	16

Access
Reset


Bit	15	14	13	12	11	10	9	8
	WPVSRC[7:0]
Access	R	R	R	R	R	R	R	R
Reset	0	0	0	0	0	0	0	0


Bit	7	6	5	4	3	2	1	0
							PADERR	WPVS
Access							R	R
Reset							0	0

Bits 15:8 – WPVSRC[7:0] Write Protection Violation Source

When WPVS = 1, WPVSRC indicates the register address offset at which a write access has been attempted.

Bit 1 – PADERR Output Pad Error (cleared on read)

Value	Description
0	No error detected during a character transfer.
1	Two successive bit periods with a difference between the data read at the output of the MOSI or NPCS0 pad buffers and the corresponding inputs driven by SPI or abnormal number of SPCK edges (or no clock edge) at the output of SPCK pad buffer in synchronous mode. This may be due to erroneous IO multiplexing configuration, external short circuits, etc.

Bit 0 – WPVS Write Protection Violation Status

Value	Description
0	No write protect violation has occurred since the last read of FLEX_SPI_WPSR.
1	A write protect violation has occurred since the last read of FLEX_SPI_WPSR. If this violation is an unauthorized attempt to write a protected register, the associated violation is reported into field WPVSRC.

The online versions of the documents are provided as a courtesy. Verify all content and data in the device’s PDF documentation found on the device product page.