35.2 Rx Buffer and FIFO Element 1

Table 35-96. Register Bit Attribute Legend
Symbol	Description	Symbol	Description	Symbol	Description
R	Readable bit	HC	Cleared by Hardware	(Grey cell)	Unimplemented
W	Writable bit	HS	Set by Hardware	X	Bit is unknown at Reset
K	Write to clear	S	Software settable bit	—	—

Name:	R1
Offset:	0x004
Reset:	0x00000000
Property:	RW


Bit	31	30	29	28	27	26	25	24
	ANMF	FIDX[6:0]
Access	RW	RW	RW	RW	RW	RW	RW	RW
Reset	0	0	0	0	0	0	0	0


Bit	23	22	21	20	19	18	17	16
			FDF	BRS	DLC[3:0]
Access			RW	RW	RW	RW	RW	RW
Reset			0	0	0	0	0	0


Bit	15	14	13	12	11	10	9	8
	RXTS[15:8]
Access	RW	RW	RW	RW	RW	RW	RW	RW
Reset	0	0	0	0	0	0	0	0


Bit	7	6	5	4	3	2	1	0
	RXTS[7:0]
Access	RW	RW	RW	RW	RW	RW	RW	RW
Reset	0	0	0	0	0	0	0	0

Bit 31 – ANMF Accepted Non-matching Frame

Bits 30:24 – FIDX[6:0] Filter Index

Bit 21 – FDF FD Format

Bit 20 – BRS Bit Rate Search

Bits 19:16 – DLC[3:0] Data Length Code

Bits 15:0 – RXTS[15:0] Rx Timestamp

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