35.1 Extended Message ID Filter Element 0
| Symbol | Description | Symbol | Description | Symbol | Description |
|---|---|---|---|---|---|
| R | Readable bit | HC | Cleared by Hardware | (Grey cell) | Unimplemented |
| W | Writable bit | HS | Set by Hardware | X | Bit is unknown at Reset |
| K | Write to clear | S | Software settable bit | — | — |
| Name: | F0 |
| Offset: | 0x000 |
| Reset: | 0x00000000 |
| Property: | RW |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| EFEC[2:0] | EFID1[28:24] | ||||||||
| Access | RW | RW | RW | RW | RW | RW | RW | RW | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| EFID1[23:16] | |||||||||
| Access | RW | RW | RW | RW | RW | RW | RW | RW | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| EFID1[15:8] | |||||||||
| Access | RW | RW | RW | RW | RW | RW | RW | RW | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| EFID1[7:0] | |||||||||
| Access | RW | RW | RW | RW | RW | RW | RW | RW | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
Bits 31:29 – EFEC[2:0] Extended Filter Element Configuration
| Value | Name | Description |
|---|---|---|
| 0 | DISABLE | Disable filter element |
| 1 | STF0M | Store in Rx FIFO 0 if filter match |
| 2 | STF1M | Store in Rx FIFO 1 if filter match |
| 3 | REJECT | Reject ID if filter match |
| 4 | PRIORITY | Set priority if filter match |
| 5 | PRIF0M | Set priority and store in FIFO 0 if filter match |
| 6 | PRIF1M | Set priority and store in FIFO 1 if filter match |
| 7 | STRXBUF | Store into Rx Buffer |