20.7 GCLK Peripheral Channel Control Mapping

Table 20-4. GCLK Peripheral Channel Control Mapping
Peripheral Channel Control Register	Peripheral:Clock
PCHCTRL[0]	OSCCTRL:DFLL48M
PCHCTRL[1]	OSCCTRL:PLL
PCHCTRL[2]	FREQM:MSR0
PCHCTRL[3]	FREQM:MSR1
PCHCTRL[4]	FREQM:REF
PCHCTRL[5]	EIC
PCHCTRL[6]	CAN0
PCHCTRL[7]	CAN1
PCHCTRL[8]	EVSYS:CH0
PCHCTRL[9]	EVSYS:CH1
PCHCTRL[10]	EVSYS:CH2
PCHCTRL[11]	EVSYS:CH3
PCHCTRL[12]	EVSYS:CH4
PCHCTRL[13]	EVSYS:CH5
PCHCTRL[14]	EVSYS:CH6
PCHCTRL[15]	EVSYS:CH7
PCHCTRL[16]	EVSYS:CH8
PCHCTRL[17]	EVSYS:CH9
PCHCTRL[18]	EVSYS:CH10
PCHCTRL[19]	EVSYS:CH11
PCHCTRL[20]	SERCOM0:SLOW SERCOM1:SLOW SERCOM2:SLOW SERCOM3:SLOW
PCHCTRL[21]	SERCOM0:CORE
PCHCTRL[22]	SERCOM1:CORE
PCHCTRL[23]	SERCOM2:CORE
PCHCTRL[24]	SERCOM3:CORE
PCHCTRL[25]	TCC0:TCC01 TCC1:TCC01
PCHCTRL[26]	TCC2
PCHCTRL[27]	TCC3
PCHCTRL[28]	SERCOM4:CORE
PCHCTRL[29]	SERCOM5:CORE
PCHCTRL[30]	TCC4
PCHCTRL[31]	TCC5
PCHCTRL[32]	TCC6
PCHCTRL[33]	ADC
PCHCTRL[34]	AC
PCHCTRL[35]	PTC
PCHCTRL[36]	CCL0
PCHCTRL[37]	CCL1
PCHCTRL[38]	USB