20.3 Block Diagram
The generation of Peripheral Clock signals (GCLK_PERIPH) and the Main Clock (GCLK_MAIN) can be seen in the Device Clocking Diagram below.
The GCLK block diagram is shown below:
The generation of Peripheral Clock signals (GCLK_PERIPH) and the Main Clock (GCLK_MAIN) can be seen in the Device Clocking Diagram below.
The GCLK block diagram is shown below:
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