35.3 Tx Buffer Element Data

Table 35-100. Register Bit Attribute Legend
Symbol	Description	Symbol	Description	Symbol	Description
R	Readable bit	HC	Cleared by Hardware	(Grey cell)	Unimplemented
W	Writable bit	HS	Set by Hardware	X	Bit is unknown at Reset
K	Write to clear	S	Software settable bit	—	—

Name:	T2
Offset:	0x08 + n*0x04 [n=0..15]
Reset:	0x00000000
Property:	RW


Bit	31	30	29	28	27	26	25	24
	DB3[7:0]
Access	RW	RW	RW	RW	RW	RW	RW	RW
Reset	0	0	0	0	0	0	0	0


Bit	23	22	21	20	19	18	17	16
	DB2[7:0]
Access	RW	RW	RW	RW	RW	RW	RW	RW
Reset	0	0	0	0	0	0	0	0


Bit	15	14	13	12	11	10	9	8
	DB1[7:0]
Access	RW	RW	RW	RW	RW	RW	RW	RW
Reset	0	0	0	0	0	0	0	0


Bit	7	6	5	4	3	2	1	0
	DB0[7:0]
Access	RW	RW	RW	RW	RW	RW	RW	RW
Reset	0	0	0	0	0	0	0	0

Bits 31:24 – DB3[7:0] Data Byte 3

Bits 23:16 – DB2[7:0] Data Byte 2

Bits 15:8 – DB1[7:0] Data Byte 1

Bits 7:0 – DB0[7:0] Data Byte 0

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