35.2 Tx Buffer Element 1

Table 35-99. Register Bit Attribute Legend
Symbol	Description	Symbol	Description	Symbol	Description
R	Readable bit	HC	Cleared by Hardware	(Grey cell)	Unimplemented
W	Writable bit	HS	Set by Hardware	X	Bit is unknown at Reset
K	Write to clear	S	Software settable bit	—	—

Name:	T1
Offset:	0x004
Reset:	0x00000000
Property:	RW


Bit	31	30	29	28	27	26	25	24
	MML[7:0]
Access	RW	RW	RW	RW	RW	RW	RW	RW
Reset	0	0	0	0	0	0	0	0


Bit	23	22	21	20	19	18	17	16
	EFC	TSCE	FDF	BRS	DLC[3:0]
Access	RW	R/W	RW	RW	RW	RW	RW	RW
Reset	0	0	0	0	0	0	0	0


Bit	15	14	13	12	11	10	9	8
	MMH[7:0]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0


Bit	7	6	5	4	3	2	1	0

Access
Reset

Bits 31:24 – MML[7:0] Message Marker Lower Byte

Bit 23 – EFC Event FIFO Control

Bit 22 – TSCE Time Stamp Capture Enable for TSU

Bit 21 – FDF FD Format

Bit 20 – BRS Bit Rate Search

Bits 19:16 – DLC[3:0] Identifier

Bits 15:8 – MMH[7:0] Message Marker Higher Byte

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