31.3.3.4 ADC Clock

The ADC clock (CLK_ADC) is scaled down from the peripheral clock (CLK_PER). The amount of scaling can be configured by the Prescaler (PRESC) bit field in the Control B (ADCn.CTRLB) register. The PGA Bias Select (PGABIASSEL) bit field in the PGA Control (ADCn.PGACTRL) register can be configured to reduce PGA power consumption depending on the ADC clock frequency.

Some of the internal timings in the ADC and the PGA are independent of CLK_ADC. To ensure correct internal timing regardless of the ADC clock frequency, a 1 µs timebase, given in CLK_PER cycles, must be defined in the TIMEBASE register in the Clock Controller (CLKCTRL) peripheral. Refer to the TIMEBASE register description in the CLKCTRL section for details.