8.8.2.4 System Configuration 0

The default value given in this fuse description is the factory-programmed value and may not be mistaken for the Reset value.

Name: SYSCFG0
Offset: 0x05
Reset: 0xD0
Property: -

Bit 76543210 
 CRCSRC[1:0]CRCSELUPDIPINCFGRSTPINCFG  EESAVE 
Access RRRRRR 
Reset 110100 

Bits 7:6 – CRCSRC[1:0] CRC Source

This bit field controls which section of the Flash will be checked by the CRCSCAN peripheral during the Reset initialization. Refer to the CRCSCAN section for more information about the functionality.
ValueNameDescription
0x0 FLASH CRC of full Flash (boot, application code and application data)
0x1 BOOT CRC of the boot section
0x2 BOOTAPP CRC of application code and boot sections
0x3 NOCRC No CRC

Bit 5 – CRCSEL CRC Polynomial Selection

This bit controls the type of CRC performed by the CRCSCAN peripheral. Refer to the CRCSCAN section for more information about the functionality.
ValueNameDescription
0x0 CRC16 CRC16 - CCITT
0x1 CRC32 CRC32 (IEEE 802.3)

Bit 4 – UPDIPINCFG Configuration of UPDI Pin at Start-Up

This bit selects the UPDI pin configuration at start-up.
ValueNameDescription
0x0 GPIO The UPDI pin is configured as GPIO
0x1 UPDI The UPDI pin is configured as UPDI with pull-up enabled on PF7

Bit 3 – RSTPINCFG Configuration of Reset Pin at Start-Up

This bit selects the pin configuration for the Reset pin at start-up.
ValueNameDescription
0x0 INPUT PF6 configured as input pin
0x1 RESET External reset with pull-up on PF6 enabled

Bit 0 – EESAVE EEPROM Saved During Chip Erase

This bit controls whether the EEPROM is erased or preserved during a chip erase. If enabled, only the flash memory will be erased by the chip erase.
ValueNameDescription
0x0 DISABLE EEPROM is erased during a chip erase
0x1 ENABLE EEPROM is preserved during a chip erase regardless of whether the device is locked or not