25.3.3.1.1 Clock Operation

The CMODE bit in the Control A (USARTn.CTRLA) register determines whether the transmission clock functions an input (Client mode) or an output (Host mode). The data input (on RXD) is sampled at the XCK clock edge opposite to the edge on which data are transmitted (on TXD), as illustrated in the figure below.

The I/O pin can be inverted by setting the Inverted I/O Enable (INVEN) bit to ‘1’ in the Pin n Control register of the port peripheral (PORTx.PINnCTRL). This setting configures which XCK clock edge is used for sampling RxD and transmitting on TxD. If the inverted I/O is disabled (INVEN = 0), the rising XCK clock edge represents the start of a new data bit, and the received data will be sampled on the falling XCK clock edge. If inverted I/O is enabled (INVEN = 1), the falling XCK clock edge represents the start of a new data bit, and the received data will be sampled on the rising XCK clock edge.