4.3 SPI Settings
The SPI Settings section configures each SPI chip select channel independently.
A tab bar at the top of this section shows CS0, CS1, CS2 and CS3. The number of enabled tabs corresponds to the number of chip select pins enabled in the Input/Output Settings table. For example, if CS0 and CS2 are enabled as I/O designations, only the CS0 and CS2 tabs will be active.
Tabs for chip select pins that are not enabled in the I/O table are dimmed and non-clickable
Tooltip: “Enable in Input/Output Settings.”
- If no chip select pin is enabled, an error message is shown: “Select at least one Chip Select pin from Input/Output Settings.”
Each active chip select tab provides the following settings:
| Field | Description |
|---|---|
| Speed | The SPI clock speed |
| Mode | The SPI mode (clock polarity and phase) |
| Active Low/Active High | The chip select polarity, with a small waveform preview |
| CS/Data Delay | A delay, in microseconds, between chip select assertion and data transfer (0–5000 μs) |
: Only one chip select tab is
active at a time—the one marked with a checkmark
icon. When reading a device configuration, only the active
chip select tab reflects the settings read from the
device. The other enabled tabs retain the settings
previously configured by the user and may be stale. When
writing a configuration, only the settings of the active
(checkmarked) tab are programmed into the device. The
additional tabs are provided for comparing and preparing
settings before selecting which chip select to
activate.